Thaslem Fathima

Software Engineer

Bengaluru, Karnataka, India8 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in power and performance engineering
  • Proficient in low-power design and validation
  • Strong background in debugging and system analysis
Stackforce AI infers this person is a Power and Performance Engineer in the Semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Power ManagementSystem On A Chip (soc)

Other Skills

DebuggingLow-power DesignSQLPythonRequirements AnalysisPerformance AnalysisWindows DebuggingSoC validationSystem Responsiveness AnalysisLauterbatch

About

Experienced Test Engineer with a demonstrated history of working in the information technology and services industry. Skilled in SQL, Python, Requirements Analysis, Performance Analysis, Windows Debugging, SoC validation, System Responsiveness Analysis , Power management and Lauterbatch.

Experience

8 yrs 3 mos
Total Experience
4 yrs 1 mo
Average Tenure
5 yrs 2 mos
Current Experience

Intel corporation

Power and Performance Engineer

Feb 2021 – Present · 5 yrs 2 mos · Bengaluru, Karnataka, India

DebuggingLow-power DesignPower ManagementSystem on a Chip (SoC)

Ust global

validation&debug engineer

Jan 2018 – Feb 2021 · 3 yrs 1 mo

Education

Anna University Chennai

Bachelor of Engineering - BE

Jan 2012 – Jan 2016

Perunthalaivar Kamarajar Girls Hr sec school

Bachelor of Engineering - BE

Jan 2012 – Jan 2016

Stackforce found 100+ more professionals with Power Management & System On A Chip (soc)

Explore similar profiles based on matching skills and experience

Bala Shiva Vishwanatham

Bala Shiva Vishwanatham

ASIC Physical Design Engineer

at MediaTek

Bengaluru, India4 yrs 11 mos exp
Physical DesignVery-Large-Scale Integration (VLSI)
Aditya Verma

Aditya Verma

Senior Lead Engineer

at Qualcomm

Bengaluru, India7 yrs 7 mos exp
Krishnendhu u.n

Krishnendhu u.n

Senior Design Engineer

at Cerium Systems

Bengaluru, India10 yrs 3 mos exp
FPGARTL Design
Shikha Shrivastava

Shikha Shrivastava

SoC Design Engineer

at Intel Corporation

Hyderabad, India6 yrs 9 mos exp
Automatic Test Pattern Generation (ATPG)Scan Insertion
Amandeep Singh

Amandeep Singh

Accumulated Expertise

at Career-Wide Experience

Roorkee, India0 mo exp
Shubhankar Das

Shubhankar Das

Lead Engineer

at Qualcomm

Faridabad, India10 yrs 1 mo exp
Devank Aeron

Devank Aeron

Design Verification Trainee

at Silicon Patterns

West Delhi, India3 yrs 10 mos exp
Functional VerificationVerification and Validation (V&V)
Sujay Jain

Sujay Jain

Senior DFT Engineer

at MediaTek

Bengaluru, India3 yrs 7 mos exp
DFTApplication-Specific Integrated Circuits (ASIC)