Barada Biswal — Software Engineer

• Self-starter with handsome years of extensive experience on Chip level/Cluster/IP verification on multimillion Gate and complex Design with multiple clocks. • Testbench and Testplan development to address the chip/block along with functional requirements with strong expertise in analyzing the design issues in the RTL. • Experienced and worked with HVLs (System Verilog/System C/UVM), HDLs (Verilog/VHDL), PLI/DPI, simulators (IUS/Questa), Scripting (Perl). • Experience in UWB, Bluetooth packet processor, RISCV, processor subsystem, MIPS processor based management module DV architecture, 10Gbit Ethernet Controller, Branch Predicted Pipelining, ASIC Controller Subsystems, Cache Coherency protocols and memory controllers. • Hands on experience on communication protocols like UART, SPI, IIC, APB, AHB, AXI, JTAG and MDIO interfaces. • Having Good Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management. • Superior written and oral communication skills and have High aptitude for digital design verification debugging skills for any protocol.

Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in ASIC and complex digital design.

Experience: 9 yrs 10 mos