Saswat Pattnayak

Software Engineer

Bengaluru, Karnataka, India1 yr 10 mos experience

Key Highlights

  • Expertise in C++ and SystemVerilog for silicon engineering.
  • Experience in Accelerator NoC Verification at Rivos Inc.
  • Strong foundation in Electrical and Electronics Engineering.
Stackforce AI infers this person is a Semiconductor Verification Engineer with strong skills in C++ and SystemVerilog.

Contact

LinkedIn

Skills

Core Skills

C++Systemverilog

Other Skills

Universal Verification Methodology (UVM)Functional VerificationDebuggingNoCVerilogPythonC (Programming Language)Keil uVisionMATLAB

Experience

1 yr 10 mos
Total Experience
1 yr 5 mos
Average Tenure
5 mos
Current Experience

Meta

Silicon Engineer

Dec 2025 – Present · 5 mos · Bengaluru, Karnataka, India · Hybrid

  • Joined via Meta acquisition of Rivos
C++SystemVerilogUniversal Verification Methodology (UVM)Functional VerificationDebuggingNoC+5

Rivos inc.

2 roles

Member of Technical Staff

Jul 2024 – Dec 2025 · 1 yr 5 mos · Hybrid

  • Accelerator NoC Verification
SystemVerilogC++

Silicon Intern

Jan 2024 – Jun 2024 · 5 mos · Hybrid

Education

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2020 – Jan 2024

Mother's Public School

Jan 2018 – Jan 2020

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