Sparsh Kachhadiya

Software Engineer

Bengaluru, Karnataka, India4 yrs 2 mos experience

Key Highlights

Expert in SystemVerilog and CPU verification.
Led critical verification projects at Rivos Inc.
Strong foundation in FPGA design and implementation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on RISC-V and SystemVerilog.

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Skills

Core Skills

SystemverilogVerilogRisc-vCpu Verification

Other Skills

C (Programming Language)Python (Programming Language)Machine LearningProgrammingC++hypervisor testplanCPU RASMP featuresUPF power-aware verificationAssertionsDebuggingCoverageFPGAEngineering

Experience

4 yrs 2 mos

Total Experience

1 yr 3 mos

Average Tenure

4 mos

Current Experience

Rivos inc.

CPU DV

Jun 2023 – Dec 2025 · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Authored hypervisor testplan and developed RISC-V AIA compliance tests verifying hypervisor-level interrupt virtualization and filtering
Led the verification of Top level CPU RAS and tested reset feature for critical errors in SOC scenarios
Verification of various MP features like A/D bit update (svadu), Native Debug, RISC-V Interrupt Controller, Clock freeze features, Thermal Hub Controller
Contributed to tape-out sign-off via GLS, UPF power-aware verification, and end-to-end coverage closure

RISC-Vhypervisor testplanCPU RASMP featuresUPF power-aware verificationCPU Verification

Intel corporation

Verification Engineer

Aug 2022 – Dec 2022 · 4 mos · Bengaluru, Karnataka, India

Writing System Verilog Assertions for Design Blocks.
Debugging Assertions in JasperGold FPV and analyzing stimuli and checker coverage of the DUT
Performing Coverage merging in VC Formal

SystemVerilogAssertionsDebuggingCoverage

Birla institute of technology and science, pilani - goa campus

Teaching Assistant

Jan 2022 – May 2022 · 4 mos

MicroProcessor & Interfacing : Guiding junior undergraduate students in the course and conducting labs on assembly language.

Redpine signals

Summer Intern

May 2021 – Jul 2021 · 2 mos · Hyderabad, Telangana, India

Implemented Full Adder through Verilog to Routing (VTR); generated netlist and produced binary
file to configure FPGA.
Investigated 2D/3D/2.5D FPGA design architecture.
Reviewed research papers to compare different FPGA architectures and FPGA tools.

VerilogFPGA