Jan 2023 – Jun 2025 · 2 yrs 5 mos

• Led verification efforts for two key IPs and a subsystem within Data flow processor based project
• Led and mentored a team of 8-12 verification engineers, resulting in on time and quality delivery of 3 SOC and achieve best rating.
• Spearheaded verification of SOC idle/standby power state flows for peripheral controller architecture, verification of cache controller,
• Integrated synopsys AXI4 VIP with testbench. Developed OVM/UVM based test cases and sequences for feature verification
• Created and implemented UVM RAL model.,subsystem testbench and test plan ensuring robust verification coverage

Nov 2020 – Dec 2022 · 2 yrs 1 mo

• Extensively worked on test and sequence development for SOC idle/standby power saving mode scenarios.
• Handled multiple variants of the SOC for power saving features.
• UPF based tesrbench understanding and debug knowledge

Mar 2019 – Nov 2020 · 1 yr 8 mos

• Trained in Zebu emulation platform from synopsys.
• Worked on SOC verification.
• worked on client project for critical power saving flows which includes clock/power gating features and soc idle/standby power management features
• hands on experience in Verdi/DVE based debugs, OVM and UVM based test/sequence development.
• Developed perl and python based scripts.
• Conducted proof-of-concept work on fault modelling verification (ISO 26262 standard compliant)

Apr 2018 – Feb 2019 · 10 mos

• FPGA RTL design , implementation , simulation & Testing for DSP Algorithems such as Digital filters, Digital down converter, BPSK Demodulator or other algorithms for satellite & RADAR receivers.
• Responsibilities-
• Leading & Managing tasks for team of 7 members
• FPGA RTL design & Simulation for DSP application
• FPGA implementation.
• Support in FPGA/SOC selection for new Hardware development. Support for FPGA/SOC pin selection in new hardware design.
• Interfaces & Architecture design of system implementation
• Support for Business Development Activity.
• Client interaction for requirement capture & Support.
• Interfaces used in Projects -
• Gigabit Ethernet, DDR2 memory, Link Port of Analog devices DSP, serial interface, RS232.
• Tools used: - Xilinx ISE Design Suit
• Test instruments used: DSO/MSO, Spectrum analyzer.
• HDL language used in projects: VHDL
• FPGAs used in projects: Xilinx Virtex-5, Spartan-6.

Oct 2016 – Mar 2018 · 1 yr 5 mos

• Responsibilities-
• FPGA RTL design & Simulation for DSP application
• FPGA implementation.
• Support for Business Development Activity
• Support for Board bring up & BSP development
• Interfaces used in Projects -
• Gigabit Ethernet,Link Port of Analog devices DSP, serial interface, RS232.
• Tools used: - Xilinx ISE Design Suit
• Test instruments used: DSO/MSO, Spectrum analyzer.
• HDL language used in projects: VHDL
• FPGAs used in project - Virtex-2, SPARTAN-3A DSP, SPARTAN-6

Aug 2015 – Sep 2016 · 1 yr 1 mo

• I was working as FPGA RTL design Engineer.
• Responsibilities-
• FPGA RTL design,Simulation & implementation on Custom FPGA boards
• System testing as per Acceptance test plan.
• Support in custom board bring up.
• Interfaces used in Projects -
• Gigabit Ethernet, DDR2 memory, Link Port of Analog devices DSP, serial interface, RS232.
• Tools used: - Xilinx ISE Design Suit
• Test instruments used: DSO/MSO.
• HDL language used in projects: VHDL
• FPGAs used in projects: Xilinx Virtex-2.

Aug 2014 – May 2015 · 9 mos · Pune Area, India

• Done final year project titled 'Ternary Analog-to-Digital converter using CNTFET'