D

Devakumar S

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 1 year of ASIC Verification experience
  • Expertise in processor verification and debugging
  • Strong foundation in UVM and SystemVerilog
Stackforce AI infers this person is a skilled verification engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogFunctional VerificationVerilog

Other Skills

Assertions based verificationsProblem solvingObject oriented verificationTests planningUVMFull chip nand flash memoryCoverage developmentUVM test-benchEthernet protocol developmentC++QuestasimSystem on a Chip (SoC)Computer Architecture

About

Computer architecture and vlsi industry, 1.Experience in Design Verification engineer with 1+ year of experience in ASIC Verification and Basics processor Verification with a passion for continuous learning and improving. 2.Experience in Processor Cores, caches, coherency and paging and TLB miss matches correction and debugging test case failures of FE,DE,EX and LS units of processor.

Experience

8 yrs 9 mos
Total Experience
2 yrs 2 mos
Average Tenure
4 yrs
Current Experience

Amd

Senior Verification Engineer

May 2022 – Present · 4 yrs · Bengaluru, Karnataka, India · On-site

  • Skills:
  • CPU Design- Assembly language
  • Assertions based verifications
  • Problem solving- Reset and clocks
  • Object oriented verification(sv and UVM) and
  • Tests planning to find the hole in RTL.
Assertions based verificationsProblem solvingObject oriented verificationTests planningUniversal Verification Methodology (UVM)SystemVerilog

Micron technology

Design Verification Engineer ||

Dec 2020 – May 2022 · 1 yr 5 mos · Hyderabad, Telangana, India · On-site

  • Worked on Full chip nand flash memory, developed Verilog/UVm based test cases to find RTL holes, Also Developed coverage for Nand features.
VerilogUVMFull chip nand flash memoryCoverage developmentFunctional Verification

Vvdn technologies

Design Verification Engineer

Apr 2020 – Nov 2020 · 7 mos · Bengaluru, Karnataka, India · Remote

  • Worked on FPGA project for Xilinx.

Blackpepper technologies pvt ltd

Design Verification Engineer

Jul 2017 – Mar 2020 · 2 yrs 8 mos · Bengaluru, Karnataka, India · On-site

  • Worked on ODC project and Development of Ethernet protocol( UVM test-bench)
UVM test-benchEthernet protocol developmentFunctional VerificationUniversal Verification Methodology (UVM)

Education

Visvesvaraya Technological University

Electrical — Electronics and Communications Engineering

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm) & Systemverilog

Explore similar profiles based on matching skills and experience

DM

Deepali M.

Accumulated Expertise

at Career-Wide Experience

Germany0 mo exp
Harjot Singh Kamboj

Harjot Singh Kamboj

Senior Design Verification Engineer

at Micron Technology

Hyderabad, India8 yrs 7 mos exp
FPGA Development
Dharmesh Gurjar

Dharmesh Gurjar

Senior Design Verification Engineer

at Qualcomm

Surat, India6 yrs 2 mos exp
Krati Agrawal

Krati Agrawal

Performance Architect

at Meta

Austin, United States8 yrs 9 mos exp
Computer Architecture
Karthikeyan J G

Karthikeyan J G

Senior Department Manager

at MediaTek

Bengaluru, India17 yrs 1 mo exp
Ravinjay Tiwari

Ravinjay Tiwari

Technical Lead

at eInfochips (An Arrow Company)

Ahmedabad, India11 yrs 4 mos exp
DARSHAN MEHTA

DARSHAN MEHTA

Lead Software Engineer

at Cadence Design Systems

Ahmedabad, India8 yrs 7 mos exp
NVM Express (NVMe)Python (Programming Language)
SV

Sireesha Vasipalli

Sr.Silicon Design Engineer

at AMD

India5 yrs 7 mos exp