Mahesh Patil

Software Engineer

Bengaluru, Karnataka, India14 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

13+ years in High Speed IO and Analog Circuit Design
Expertise in multiple PHYs for high-speed protocols
Post silicon debug experience in power management circuits

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Analog Circuit Design and High Speed IO.

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Skills

Core Skills

Analog Circuit DesignHigh Speed IoPower Management

Other Skills

ValidationCircuit ExecutionPost Silicon CharacterizationVLSICircuit DesignCadence VirtuosoVerilogRTL designMentor EldoSynopsys NanosimCalibre RVECalibre (DRC, LVS, RCX, Latchup, Stress)Magma FinesimproCharacterizationLVS

About

High Speed IO and Analog Circuit Designer with 13+ Years of Experience Worked on a variety of PHYs for High Speed Serial IO protocols such as USB4 TPC (CIO80, CIO40), USB3, TBT, PCIE1-6, UXI, DMI, HDMI2.1, DP2.0, eDP, MIPI DPHY with Applications in Servers & Client products(Tablets, Smartphones, Ultrabook, Detachables, TypeC Hub). Includes multiple Process technologies such as Intel 18A GAAFET, 7nm FINFET(I3), 10nm/14nm FINFET for IOs and UMC 65nm for Async SRAM. Designed & validated a wide range of High Speed IO & Analog building blocks including Transmitters (Driver, Predriver, Retimer, Serializer), Receivers (AFE,CTLE,VGA,DFE,DCO) and Power management circuits(Voltage Regulators, Bandgap references, Current references, Amplifiers, Comparators, Charge Pumps). Post silicon debug experience for Bench Validation on HSIO products and Async SRAM power management block characterization.

Experience

14 yrs 9 mos

Total Experience

7 yrs 4 mos

Average Tenure

11 yrs 7 mos

Current Experience

Intel corporation

3 roles

Senior Staff Analog Design Engineer

Promoted

Jun 2022 – Present · 3 yrs 11 mos

Project1: RX DCO & Clockpath Design and validation
HSIO PHY for USB4 TPC,USB3,TBT,DP2.0,eDP,HDMI 2.1
Process technology: Intel I3 7nm FINFET
Project2: RX DCO Design and validation
HSIO PHY for USB4 TPC,USB3,TBT,DP2.0,HDMI2.1
Process technology: Intel 18A GAAFET
Performing additional role as Circuit execution lead to ensure circuit team deliverables to other domains(RTL Logic, RTL VAL, RTL DFX, SD & PT, Layout, BMOD, MSV, Signal Integrity & Power Delivery, System, Reliability signoff)

Analog Circuit DesignHigh Speed IOValidationCircuit Execution

Staff Analog Design Engineer

Aug 2017 – May 2022 · 4 yrs 9 mos

Project1: RX DFE Retimer(Forward path) & S2P Design and Validation
HSIO PHY for PCIE1/2/3/4/5/6 & UXI
Process technology: 7nm FINFET(INTEL I3)
Project2: RX AFE CTLE & VGA Design and Validation
HSIO PHY for USB-TPC/DP/HDMI
Process technology: 10nm CMOS FINFET
Project3: TX AFE Circuit Design & Validation
Serial I/O DISPLAY PHY: DP1.4/eDP/HDMI2.0
Process technology: 14nm CMOS FINFET

Analog Circuit DesignValidationHigh Speed IO

Senior Analog Design Engineer

Aug 2014 – Jul 2017 · 2 yrs 11 mos

Project1: TX AFE Circuit design & validation(Driver, Predriver, 2:1-Serializer)
Serial I/O DISPLAY PHY: HDMI2.0, DP1.4, eDP & MIPI DPHY
Process technology: 10nm CMOS FINFET
Project2: CL - Calibration/Observation circuits (Irefgen, Vrefgen, Comparator, Amplifiers, AMON, DMON)
Serial I/O DISPLAY PHY: HDMI 2.0, DP1.4, eDP & MIPI DPHY
Process technology: 10nm CMOS FINFET

Analog Circuit DesignValidationHigh Speed IO

Cypress semiconductor corporation

Senior Elect Design Engineer

Jun 2011 – Jul 2014 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Power management IP in Asynchronous SRAM chip
Circuits designed/worked on: Bandgap Voltage reference, Current reference, Active Voltage regulators for SRAM, Comparators, Amplifiers, Subtractor circuits.
Post Silicon Bench Characterization of Analog blocks such as Load/Line regulation, Voltage/Current measurements using keithley, pic-probing for debug porpose.

Power ManagementAnalog Circuit DesignPost Silicon Characterization