Ashok kumar Dabbugunta

Director of Engineering

Andhra Pradesh, India27 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

20+ years in semiconductor architecture and design
Led global teams to deliver high-impact projects
Expert in multi-die and multi-chiplet systems

Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in advanced processor architectures.

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Skills

Core Skills

ArchitectureDesignSoc DevelopmentDesign Verification

Other Skills

Intel/AMD x86RISC-VARM processor architectureson-chip coherent scalable fabric architectureshigh-speed I/O technologiesPCIe Gen6.0CXL3.0UCIe1.0200G Ethernet100G high-speed PHYDDR5-8.8GTs/MCR12.8GTsServer RAS flowssecurity protocols SGXTDXMKTME

About

Results-oriented Engineering Manager with over 20+ years of experience in Intel/AMD x86, RISC-V, and ARM processor architectures. Proficient in on-chip coherent scalable fabric architectures and high-speed I/O technologies, including PCIe Gen6.0, CXL3.0, UCIe1.0, 200G Ethernet, 100G high-speed PHY, DDR5-8.8GTs/MCR12.8GTs, Server RAS flows and security protocols SGX, TDX, MKTME, VAD and SDL. Proven track record in Architecture, Design, Verification, Emulation, Post Silicon validation and productizing complex multi-die, multi-chiplet, and multi-socket systems across diverse domains, including Server, Networking, Edge, Client-PC, and Automotive. Adept at leading large, global engineering teams to drive innovation and deliver high-impact projects throughout their lifecycle. Committed to engineering excellence and fostering a culture of continuous improvement.

Experience

27 yrs 11 mos

Total Experience

4 yrs 7 mos

Average Tenure

7 yrs 2 mos

Current Experience

Intel corporation

Engineering Manager, Networking and Xeon SoC Products

Apr 2019 – Present · 7 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Led the development of Intel’s next-generation low-power Networking and Xeon processor SoC products, overseeing a DV team of simulation/emulation engineers. Spearheaded the successful tape-out of the Granite Rapids-D product and the execution of the world’s first multi-die product first silicon success with the latest technology node.

Intel/AMD x86RISC-VARM processor architectureson-chip coherent scalable fabric architectureshigh-speed I/O technologiesPCIe Gen6.0+13

Rambus

Senior Manager

Sep 2015 – Apr 2019 · 3 yrs 7 mos · Bangaluru

Successfully led a team of 40 engineers in the development of PCIe Gen4 Switch SoCs and taped out 2 SoC’s.

PCIe Gen4 Switch SoCsSoC Development

Amd

Design Verification Manager

Dec 2010 – Sep 2015 · 4 yrs 9 mos · Hyderabad Area, India

Drove the project planning and execution for multiple client-SoCs with a team of 30 verification and validation engineers. Architected and implemented a scalable verification environment for SoC, subsystem, and block-level test benches. Integrated Veloce and Palladium emulation platforms to enable pre-silicon validation for all Enterprise SoC processors.

Design VerificationVerification environmentVelocePalladium emulation platforms