Aditya Kumar Prusty

Software Engineer

Bengaluru, Karnataka, India5 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in PCIE verification and power management.
Proficient in SystemVerilog and UVM methodologies.
Strong background in testbench optimization and design patterns.

Stackforce AI infers this person is a Design Verification Engineer with expertise in PCIE and digital circuit design.

Contact

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)Pcie VerificationDesign PatternsDesign Verification

Other Skills

Testbench ReusabilityAbstraction Level ImprovementPower ManagementData Link LayerTest Bench OptimizationDesign Verification Utility LibraryUMC-IP VerificationLogic GatesPython (Programming Language)Test PlanningAssertionsAssertion Based VerificationPerlMicrosoft OfficeC (Programming Language)

About

PCIE Verif- Nvidia SV and UVM Based Random, Constrained Random, Coverage Driven Verification and UVC design. Experience in Debugging, Bug reporting and Bug fix validation, Regression run . Verification of PCIE DL layer and Power Management. TB refactoring for better reusability of IP in FSTB. Perl Based Ground work for Coverage grading and storing the graded tests for the next iteration of regression to run and add to coverage. Perl based aspertion checks to prevent check ins that don't fit the criteria.

Experience

5 yrs 3 mos

Total Experience

2 yrs

Average Tenure

3 yrs 8 mos

Current Experience

Nvidia

2 roles

Senior Engineer(IC3)

Promoted

Apr 2024 – Present · 2 yrs 1 mo · Bengaluru, Karnataka, India

Using Design Patterns to improve the testbench reusability and improve the abstraction level of the testbench as part of HSIO-PCIE team.

Design PatternsTestbench ReusabilityAbstraction Level ImprovementSystemVerilogUniversal Verification Methodology (UVM)

Engineer II(IC2)

Oct 2022 – Apr 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India

PCIE-IP Gen6
Power Management, Data Link Layer.
Test Bench Optimisation based on Different design pattern implementations. Creating Design Verification Utility Library for reuse.

Power ManagementData Link LayerTest Bench OptimizationDesign Verification Utility LibraryPCIE VerificationDesign Patterns