Dec 2022 – Jun 2025 · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

• Member of the Architecture team responsible for product definition SoC targeted for Mobile Backhaul.
• Development of Micro-Architecture and design specification of Micro-blocks in Convergence Layer for the Mobile backhaul SoC
• System-C Model for WiFi SoC and integration with router model for performance evaluation in the design phase.
• System-C model for 5g-NR O-RAN Fronthaul with emphasis on UL-DL packetization and packet scheduling to data packets. The model is targeted to make design optimization for data buffer size, data load on the fronthaul ports and bandwidth capacity, scheduling parameters and optimal mapping of spectrum container to fronthaul ports for efficient bandwidth utilization.
• Python based tools/scripts for performance data analysis and data visualization.

Oct 2013 – Nov 2022 · 9 yrs 1 mo · Bangalore · On-site

• Leadership in the design of development of Controller FW with critical contribution in developing strategies of memory node integration, performance and reliability to enhance the memory life and data integrity
• Lead and managed a team to develop Sysyem-C model for Performance validation and idea exploration for performance optimization and data reliability
• Key contributor to Flash Controller SoC for various complex IP module design and HW Accelerator blocks for system optimization and performance enhancements
• Leadership in architecture and design level for various Flash products with various capacity, memory node density and host interfaces (SATA, USB2.0/3.2, PCIe/NVMe)
• Mentored a group of engineers for innovation, invention disclosures and fling patents

Nov 2009 – Sep 2013 · 3 yrs 10 mos

• Managed teams responsible in development and maintenance of multiple SoC products, including system development, FW/SW development, validation lab, defect tracking, managing customer issues,
• Lead a team of engineers developing FW for 3rd generation AVDSL chip targeted for high density DSLAM Line card solutions and integrated data processing component supporting DSL variants like ADSL1, ADSL2/2+, VDSL2.
• Managed/lead teams of Engineers in developing highly optimized Firmware on a SoC with multi-core specialized packet processor (NPU) for DSLAM and L2 switches
• Lead contributor in the architecture team for processor micro-architecture in packet processor, processor cluster, event mechanisms in HW for multi-threaded/core development.
• Lead contributor in the architecture team for design and concept development for SoC based Home-Gateway solutions

Jan 2006 – Nov 2009 · 3 yrs 10 mos · Bengaluru, Karnataka, India · On-site

• Managed/lead teams of Engineers in developing highly optimized Firmware on a SoC with multi-core specialized packet processor (NPU) for DSLAM and L2 switches
• Lead contributor in the architecture team for processor micro-architecture in packet processor, processor cluster, event mechanisms in HW for multi-threaded/core development.

Jan 2000 – Jan 2006 · 6 yrs

• Developed networking solution on Intel NPU (IXP)
• Worked on TOE application, IO acceleration and virtualization
• Profiling and optimization of multi-threaded embedded application on Multi-core IA(Intel Architecture processor)

Jan 1997 – Jan 2000 · 3 yrs

Jan 1994 – Jan 1996 · 2 yrs