Pankaj Gramopadhye

Product Engineer

Bengaluru, Karnataka, India8 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in Analog Circuit Design and VLSI.
Proven track record in high-speed circuit design.
Strong background in post-silicon debugging.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in high-speed circuit design and VLSI.

Contact

Skills

Core Skills

Analog Circuit DesignVery-large-scale Integration (vlsi)

Other Skills

VerilogVerilog-ACMicrosoft OfficeMatlabCadence VirtuosoCircuit DesignHigh Speed clock path DesignTransmitter Duty Cycle CorrectorLDO DesignESD DesignPLL DesignVoltage standing wave clockingCMOS driver design

Experience

8 yrs 11 mos

Total Experience

3 yrs 6 mos

Average Tenure

1 yr 11 mos

Current Experience

Cadence design systems

Lead Design Engineer

Jul 2024 – Present · 1 yr 11 mos · Hybrid

Analog Circuit DesignVery-Large-Scale Integration (VLSI)VerilogVerilog-ACMicrosoft Office+3

Amd

SeniorSilicon Design Engineer

May 2023 – Jul 2024 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

2 roles

Circuit Design Engineer

Jul 2018 – May 2023 · 4 yrs 10 mos

Multiprotocol Phy (MAX 28Gbps NRZ/PAM4):
High Speed clock path Design : Owned transmitter Jitter budget for Ethernet (28Gbps) and
PCIE (16Gbps) applications. Focused on supply noise and non-supply noise jitter component. Optimized power supply noise induced Jitter for transmitter clock path and data path. Worked on clock path Random Jitter. PSN DJ, RJ, TX DCD Error (Even-Odd jitter) and Jitter amplification are part of overall TX Jitter Budget.
Transmitter Duty Cycle Corrector: Implemented and optimized transmitter duty cycle corrector for 16GHz clock. Worked on finding required DC range considering both systematic and mismatch variation. Implemented AC coupled inverter with feedback resistor for correcting duty cycle range. Designed current DAC to control bias current of AC coupled inverter. This DCC designed for correcting +/- 5% duty cycle range across PVT's.
LDO: This LDO was powering transmitter clock path. PSRR improvement helped in improving transmitter clock path supply noise jitter. LDO was designed for 1V with 40mA load current support.
ESD: Owned I/O’s ESD and DPZ . Designed ESD for Transmitter, receiver, and common lane pads. Worked on ESD timer circuits. Designed DPZ for system exposed IO pads.
PCIE Gen6:
Global Clock distribution: Worked on PLL output clock path for 16Ghz. Designed Voltage standing wave clocking for lower jitter performance. Implemented CMOS driver with channel to distribute 16GHz clock across 4 transmitters. Channel is designed for 1.2mm with distributed inductor termination. Analyzed channel terminations options like short circuit, open circuit, lumped inductor, and distributed inductor. Distributed inductor termination is used for final design based on clock swing quality.
DP1.4:
Post silicon Debug: Involved in post silicon debug for Display IP. False triggering of clamps observed during supply sequencing. Provided and implemented solutions for Common Lane pad ESD issue.