Saurabh Katre

Software Engineer

Bengaluru, Karnataka, India4 yrs 8 mos experience

Key Highlights

  • M.Tech graduate from IIT Bhubaneswar.
  • Experienced in VLSI design and verification.
  • Proficient in SystemVerilog and UVM methodologies.
Stackforce AI infers this person is a VLSI Engineer with expertise in verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Verification Engineering

Other Skills

SVRALUVMUniversal Verification Methodology (UVM)AXIPCIeSystemVerilogVerilogModelSimCadenceQuartus PrimeXilinx Vivado

Experience

4 yrs 8 mos
Total Experience
1 yr 11 mos
Average Tenure
9 mos
Current Experience

Sivaltech

Senior Staff Engineer

Aug 2025 – Present · 9 mos · Banglore · On-site

Proxelera

Engineer - VLSI Design (DV)

Nov 2023 – Aug 2025 · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

  • Client - Rivos

Amd

Verification Engineer

Jul 2020 – Aug 2022 · 2 yrs 1 mo · Hyderabad, Telangana, India · On-site

SVRALVerification Engineering

Education

Indian Institute of Technology Bhubaneswar (IIT Bhubaneswar)

M.Tech — Electronics and Communications Engineering

Jan 2018 – Jan 2020

Yeshwantrao Chavan College of Engineering Nagpur

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2011 – Jan 2015

Gondia Public School, Gondia.

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