Feb 2015 – May 2018 · 3 yrs 3 mos · Greater Bengaluru Area

• Project Title: FDD/WCDMA *** IP & High-Speed Sub-system Verification in System Verilog and UVM.
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• Project Title: Smart Phone SoC Modem Low Power Verification: ( ARM & MIPS) Based SoC
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• Project Title: IP/Block Level Verification in UVM.
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• Roles & Responsibilities:
• 1. Testbench architecture development from scratch.
• 2. Feature extraction, Test plan development & writing random test-scenarios.
• 3. Functional coverage development and closure.
• 4. Checker/Assertion development and Debug.
• 5. Documentation of every stage [start to sign-off].
• Early stages of RTL Power Optimization Verification for Smartphone & Modem Projects.
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• Applying Low Power Verification techniques in SoC [Smart Phone] in achieving the best power numbers. [ARM & MIPS based SoC (System on Chip) Verification at RTL level].

Jun 2011 – Jan 2015 · 3 yrs 7 mos · Bangalore

• Project Title: Network on Chip (NoC) - Verification both SoC level & module level
• Description: The Network processor(NOC) is used to process different tasks in different planes of network processing applications. A network processor can be utilized in two different planes that that differ in the speed and manner they handle incoming packets; namely data plane and control plane.In the data plane simple tasks are performed at line speed, and most packets follow the fast/same path through the network processor that required very little processing. In the control plane exceptional packets and complex routines are handled.
• Processor used : Tensilica Xtensa LX3
• Role:
• SoC level Verification Connectivity(Among 24 processor cores , Core to IP ,Core to Memory connectivity testing)Module level Verification of System Packet Interface [SPI] which supports 256 ports and compression- decompression.
• Module level Test case development in UVM.
• Emulation on Mentor Veloce Quattro
• Rapid prototyping on Aldec platform
• Methodologies Universal Verification methodology (UVM)
• Tools used: Aldec Rivera Pro 2013
• Highlights:
• SoC level Verification
• Boot up sequence verification
• Data Flow
• UVM SCEMI 2.0 Transactor based Module level verification