Manivannan Parandaman

DevOps Engineer

Chennai, Tamil Nadu, India14 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SoC and Functional Verification.
  • Proven track record in low power verification techniques.
  • Strong leadership experience in engineering roles.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SoC and Functional Verification.

Contact

Skills

Core Skills

SocFunctional Verification

Other Skills

System on a Chip (SoC)SystemVerilogUVMLow Power VerificationVerificationEngineering LeadershipCVerilogC++VLSIMatlabWindowsLinuxModelSimJava

About

To work in a globally competitive and challenging environment that yields the twin benefits of the job satisfaction and a steady-paced professional growth.

Experience

14 yrs 7 mos
Total Experience
4 yrs 10 mos
Average Tenure
7 yrs 9 mos
Current Experience

Qualcomm

3 roles

Senior Staff Engineer/ Manager

Promoted

Nov 2024Present · 1 yr 5 mos

SoCFunctional Verification

Staff Engineer

Nov 2020Oct 2024 · 3 yrs 11 mos

Functional VerificationSystem on a Chip (SoC)SoC

Lead Engineer

Jun 2018Oct 2020 · 2 yrs 4 mos

Mediatek

Senior Engineer

Feb 2015May 2018 · 3 yrs 3 mos · Greater Bengaluru Area

  • Project Title: FDD/WCDMA *** IP & High-Speed Sub-system Verification in System Verilog and UVM.
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  • Project Title: Smart Phone SoC Modem Low Power Verification: ( ARM & MIPS) Based SoC
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  • Project Title: IP/Block Level Verification in UVM.
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  • Roles & Responsibilities:
  • 1. Testbench architecture development from scratch.
  • 2. Feature extraction, Test plan development & writing random test-scenarios.
  • 3. Functional coverage development and closure.
  • 4. Checker/Assertion development and Debug.
  • 5. Documentation of every stage [start to sign-off].
  • Early stages of RTL Power Optimization Verification for Smartphone & Modem Projects.
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  • Applying Low Power Verification techniques in SoC [Smart Phone] in achieving the best power numbers. [ARM & MIPS based SoC (System on Chip) Verification at RTL level].

Tata consultancy services

Verification Engineeer

Jun 2011Jan 2015 · 3 yrs 7 mos · Bangalore

  • Project Title: Network on Chip (NoC) - Verification both SoC level & module level
  • Description: The Network processor(NOC) is used to process different tasks in different planes of network processing applications. A network processor can be utilized in two different planes that that differ in the speed and manner they handle incoming packets; namely data plane and control plane.In the data plane simple tasks are performed at line speed, and most packets follow the fast/same path through the network processor that required very little processing. In the control plane exceptional packets and complex routines are handled.
  • Processor used : Tensilica Xtensa LX3
  • Role:
  • SoC level Verification Connectivity(Among 24 processor cores , Core to IP ,Core to Memory connectivity testing)Module level Verification of System Packet Interface [SPI] which supports 256 ports and compression- decompression.
  • Module level Test case development in UVM.
  • Emulation on Mentor Veloce Quattro
  • Rapid prototyping on Aldec platform
  • Methodologies Universal Verification methodology (UVM)
  • Tools used: Aldec Rivera Pro 2013
  • Highlights:
  • SoC level Verification
  • Boot up sequence verification
  • Data Flow
  • UVM SCEMI 2.0 Transactor based Module level verification

Education

Anna University Chennai

Master of Engineering (MEng) — Instrumentation Technology/Technician

Jan 2009Jan 2011

Kendriya Vidyalaya

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