Adithyan R

Product Engineer

Palghat, Kerala, India4 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in RTL quality checks and synthesis.
Proficient in Perl scripting for automation.
Strong collaboration with RTL teams for CDC resolution.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL quality assurance and automation.

Contact

Skills

Core Skills

CdcFevAutomationLogic SynthesisSynthesis

Other Skills

Root CausePerlDebuggingShell ScriptingInterpersonal SkillsProblem SolvingElectronic EngineeringStatic Timing AnalysisFormal VerificationEngineeringEnglishResearchCommunication

About

I am a System-on-Chip (SoC) Design Engineer with more than years of experience specializing in RTL quality checks. My expertise lies in performing thorough synthesis, STA based checks LEC, and CDC analysis using the latest technologies, specifically in TSMC and Intel nodes. Additionally, I have strong skills in Perl scripting, which I utilize to automate tasks and enhance efficiency in SoC design workflows.

Experience

4 yrs 9 mos

Total Experience

4 yrs 9 mos

Average Tenure

4 yrs 9 mos

Current Experience

Intel corporation

2 roles

SoC Design Engineer

Aug 2021 – Present · 4 yrs 9 mos · Bengaluru, Karnataka, India

1. CDC (Synopsys SpyGlass CDC)
Assumed responsibility for the closure of CDC (Clock Domain Crossing) issues within a subsystem, ensuring robust synchronization and proper data integrity.
Collaborated closely with RTL teams to identify and resolve CDC violations, applying industry best practices and methodologies.
2. FEV(Cadence Conformal Equivalence Checker)
Worked on fev_lite and fev_sim2syn. Currently enhancing my knowledge on fev_rtl2syn.
Took charge of setting up flows for Front-End Verification (FEV) in various projects.
Conducted thorough debugging and troubleshooting activities to resolve issues encountered in FEV.
3. Perl Scripting for Data Mining and Report Generation
Developed a comprehensive Perl script for performing data mining and generating reports at both the top-level and partition-level of the design.
Automated the extraction and consolidation of data, including debug-related information, into a centralized system using Splunk, enabling easy access and visualization for the entire team.
Successfully streamlined the analysis and reporting process, saving significant time and effort for the team.
4. Synthesis (Synopsys Fusion Compiler)
Provided crucial support to other teams during demanding timelines, assisting with synthesis tasks and ensuring the delivery of high-quality design collaterals before project milestones.

Root CausePerlCDCFEV

Summer Intern

May 2020 – Jul 2020 · 2 mos · Bangalore Urban, Karnataka, India

1. Synthesis Exploration and APR Flow
Demonstrated a strong curiosity and aptitude for learning by actively exploring the APR (Automatic Place and Route) flow in SoC design.
Acquired a solid understanding of the fundamentals of synthesis, including key concepts and methodologies.
2. Perl Scripting for Data Mining and Dashboard Generation
Developed a powerful Perl script to automate data mining from logs and reports generated by multiple tools used for RTL Quality checks and Synthesis.
Successfully extracted relevant information and synthesized it into a concise Excel spreadsheet, significantly improving the efficiency and ease of debug for the team.

PerlShell Scripting