Pooja Mishra — Product Engineer
Reliable and resourceful VLSI Design Engineer with 5+ years of working experience. Currently positioned as SoC Design Engineer at Google. Current responsibilities include clock architecture design of TPU SoC and IP Integration Prior I have worked on IP and subsystem integration into the server SoC and memory(RF and SRAM) integration. Experience with end to end Formal verification of design. Hands on experience with leading Integration tools, formal verification tools and RTL Power Estimation and Reduction. Skilled in System Verilog, SVA, Verilog, Perl, tcl, C, Digital Electronics and Basic Electronics. Have a working knowledge of the tools synopsis Core tool, VCS, verdi, Power Artist, Jasper Gold, Cadence encounter, cadence virtuoso, xilinx, orcad. Result oriented, self-driven, highly motivated, smart and hungry to learn new technologies, methodologies, strategies and processes.
Stackforce AI infers this person is a VLSI Design Engineer specializing in SoC architecture and integration.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 8 mos
Skills
- Soc Design
- Integration
Career Highlights
- 5+ years of experience in VLSI design.
- Expert in SoC design and integration.
- Proficient in formal verification and RTL power estimation.
Work Experience
Silicon SoC RTL Engineer (1 yr 5 mos)
Intel Corporation
SoC Design Engineer (4 yrs 3 mos)
Graduate Technical Intern (1 yr 2 mos)
Education
Master of Technology - MTech at Nirma University
bechlors of engineering at Ahmedabad Institute Of Technology
