Pragya Aggarwal

Software Engineer

Bengaluru, Karnataka, India8 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in VLSI design verification methodologies.
Strong background in UVM and System Verilog.
Proven track record in managing complex verification projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and functional verification.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)Functional Verification

Other Skills

Ethernet Bridge IP VerificationVerification StrategyTestbench InfrastructureTest-plan DevelopmentBFM DevelopmentUVMRISC-V Instruction Set ArchitectureOpen-Source Google DV Random Instruction GeneratorSpike ISA SimulatorDaily RegressionsCoverage AnalysisStatus ReportingSMEM VerificationDebug Subsystem VerificationSOC Testbench Management

About

I am working as a Design Verification Engineer with Meta having strong interest in the field of VLSI. I hold a good understanding of UVM and System Verilog langauge. I possess experience of verifying subsystem and system level blocks by using UVM and formal verification. I have a good understanding of various AMBA protocols. I also possess a strong knowledge on the micro controllers and have carried out multiple projects during my under graduation using them. I have completed my under graduation with Bachelor of Engineering (BE) focused in Electronics and Communication from Thapar Institute of Engineering and Technology with 8.79 CGPA.

Experience

8 yrs 10 mos

Total Experience

3 yrs 10 mos

Average Tenure

1 yr 1 mo

Current Experience

Intel corporation

Pre Si Verification Engineer-Design Architect

Aug 2022 – Apr 2025 · 2 yrs 8 mos · Bengaluru, Karnataka, India · On-site

Ethernet Bridge IP Verification
o Managing the verification of Ethernet Bridge IP - defined complete Verification Strategy and Testbench Infrastructure
o Developed complete Test-plan along with handling its execution.
o Responsible for developing the initial BFM for custom MAC interface using UVM.
o Coding of Test scenarios and debug failures
o Managing task assignment and execution for a team of 4.
RISC-V Processor Verification
o Developed understanding on the RISC-V Instruction Set Architecture(ISA).
o Understanding of Open-Source Google DV Random Instruction Generator(RIG) and Spike ISA simulator
o Generating different instruction set sequences and verifying all possible scenarios including exceptions, interrupts and custom instructions.
o Managing the daily regressions, coverage analysis and status reporting.
o Complete SMEM verification for RISC-V SOC test-chip

Ethernet Bridge IP VerificationVerification StrategyTestbench InfrastructureTest-plan DevelopmentBFM DevelopmentUVM+9

Nxp semiconductors

4 roles

Lead Design Verification Engineer

Apr 2022 – Jul 2022 · 3 mos

- Mentoring interns on SOC Verification and Debug-Subsystem Ramp-up.

Senior Design Verification Engineer

Promoted

Jul 2020 – Apr 2022 · 1 yr 9 mos

Complete Debug-Subsystem verification
o Handled complete ownership for Debug subsystem verification across multiple SOCs.
SOC Testbench ownership
o Responsible for managing the testbench for a SOC, maintaining coverage flow, regression management
o Developed PERL/shell scripts to automate the RTL regression run flow and generate data reports
o Developed scripts for auto-generation of waveforms for failing test cases in smoke regression
Formal Verification
o Verified a complete glue logic(ATB to internal protocol converter) using formal verification - Developed Test-plan, coded Assertions, hooked ATB Synopsys VIP, coverage analysis

Debug Subsystem VerificationSOC Testbench ManagementPERL/Shell ScriptingFormal VerificationFunctional Verification

Design Verification Engineer

Jul 2017 – Jun 2020 · 2 yrs 11 mos

SOC Verification Engineer
Debug-Subsystem verification
o Created a verification plan and developed test cases for verification of Debug Subsystem based on ARM debug architecture using UVM
o Complete understanding of ARM-based debug components including DAP architecture, debug trace
(ITM, ETM, TPIU, SWO), ECT (CTI and CTM)
o Developed hands-on knowledge of AMBA protocols – AHB, APB, ATB and basics of AXI
o Complete understanding of the JTAG interface concerning debug domain.
o Worked on the formal verification for CTI-CTM connections across the SOC using the Verdi tool and written PERL script to make this flow reusable across different SOCs.
o GLS (Gate Level Simulations) debugs for failures.
IP Verification Engineer
ACE to ATB converter verification
o Created test plan and developed UVM based testbench for quality verification
o Acquired good knowledge of ATB protocol
OTP(One Time Programmable) Memory Block verification
o Successfully verified the OTP memory block by developing self-checking test cases using UVM
o Developed understanding of the basic working of communication protocols like I2C and SPI