Dinesh Reddy

Software Engineer

San Jose, California, United States7 yrs 1 mo experience

Key Highlights

Expert in Functional Verification and RTL Design.
Proven track record in UVM based verification.
Strong leadership experience in product development.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong expertise in RTL design and functional verification.

Contact

Skills

Core Skills

Functional VerificationRtl Design

Other Skills

UVMTest plan developmentRegression task listsCoverage reportsAssertions codingTest sequences developmentPower-Aware Verification EnvironmentPower-Aware VerificationSystem VerilogUniversal Verification Methodology (UVM)Computer ArchitectureVerilog HDLPythonCC++

Experience

7 yrs 1 mo

Total Experience

2 yrs 9 mos

Average Tenure

10 mos

Current Experience

Sandisk

2 roles

Principal Engineer, Product Development Engineering

Promoted

Aug 2025 – Present · 10 mos · San Francisco Bay Area

Staff Engineer, Product Development Engineering

May 2020 – Aug 2025 · 5 yrs 3 mos · San Francisco Bay Area

Western digital

2 roles

Staff Product Design Engineer

Promoted

Jul 2022 – Feb 2025 · 2 yrs 7 mos · Milpitas, California, United States

Senior Product Design Engineer

May 2020 – Jul 2022 · 2 yrs 2 mos · Milpitas, California, United States

Intel corporation

Graduate Technical Intern

Mar 2019 – Mar 2020 · 1 yr · Folsom, California Area

Performed UVM based verification of one DDR PHY IP and assisted in developing Test plan (Verdi HVP) for DDRx/LPDDRx from JEDEC Specification.
Set up weekly regression task lists and automated merging of (.vdb) coverage files using Synopsys URG tool to generate Weekly Coverage reports. Identified holes in functional Coverage and improved tests to hit the uncovered bins. Also, coded assertions to check behavior of RTL Design.
Developed test sequences to test PHY supporting DDRx, LPDDRx technologies and worked on debugging failures from the SoC testing.
Developed test sequence to generate VCDs for different DDRx/LPDDRx frequencies to help facilitate the Power Analysis tool.
Brought up the Power-Aware (UPF) Verification Environment in sync with the GLS netlist and ran regressions.

UVMTest plan developmentRegression task listsCoverage reportsAssertions codingTest sequences development+3