Usirikayala Saidulu

Software Engineer

Bengaluru, Karnataka, India13 yrs 8 mos experience

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Proven track record in Netlist to GDSII implementation.
Strong background in VLSI and ASIC design methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisTiming Analysis

Other Skills

Netlist to GDSIITiming BudgetingDesign ImplementationArea CalculationDRC ManagementPNRRtl to gdsEMIRCTSRoutingFloorplanningPOWERPLANINGTcl-TkPython (Programming Language)FUSION COMPILER

About

CAREER OBJECTIVE: Looking for an opportunity to work as a Physical Design Engineer in dynamic work environment.

Experience

13 yrs 8 mos

Total Experience

Average Tenure

Current Experience

Samsung semiconductor

Senior Staff Engineer

Jul 2021 – Present · 4 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Physical DesignStatic Timing Analysis

Intel corporation

Physical Design Engineer

Aug 2012 – May 2021 · 8 yrs 9 mos · Bengaluru Area, India

Responsibilities:
Responsible for implementing Netlist to GDSII
Implementing the design for calculating area and to reduce the size of the blocks with good utilization numbers
Blocks are critical in both congestion and timing need to close the blocks with minimum drc’s and timing numbers at route stage to take the design to Eco stage.
Provide information to the front end team about the quality of the netlist and issues those need to be addressed.
Working on constraints and timing budgeting for IO paths to meet timing at top leve provide good database for top level.

Netlist to GDSIITiming BudgetingDesign ImplementationArea CalculationDRC ManagementPhysical Design+1