P

Prashanth Chokkarapu

Director of Engineering

Bengaluru, Karnataka, India13 yrs experience

Key Highlights

  • Over 10 years of experience in Physical Design.
  • Expert in driving projects with high-quality deliverables.
  • Strong track record with clients like AMD, Google, and ARM.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in Physical Design and VLSI.

Contact

Skills

Core Skills

Physical Design

Other Skills

Static Timing AnalysisPhysical VerificationTimingIRDRCLVSProcess ImprovementC++VerilogTCLCSystemVerilogSoCASICFirmware

About

>>> Senior Technical Manager at synapse with 10+ years of experience in the Physical Design domain. Self-motivated, data oriented loves smart work over hard work, walks an extra mile to achieve excellence, capable of working in a team and to work individually. Organized and expert in driving project with track records of producing high-quality deliverables within timeline and budgetary constraints. Self Motivated, Enthusiastic, Creative, Dedicated, Fun Loving and Confident are the words that best describes me.

Experience

13 yrs
Total Experience
--
Average Tenure
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Current Experience

Synapse design inc.

4 roles

Senior Technical Manager

Promoted

Mar 2026Present · 3 mos

Technical Manager

Jul 2022Mar 2026 · 3 yrs 8 mos

  • AMD, Google and ARM are the clients

Technical Lead

Jan 2021Jul 2022 · 1 yr 6 mos

Module Lead

Mar 2018Jan 2021 · 2 yrs 10 mos

  • Responsible for leading a team to tapeout their respective blocks. Apart from that, I have other individual contributions like full chip STA and physical verification tasks.

Amd

Senior Physical Design Engineer

Jan 2017Mar 2018 · 1 yr 2 mos · Hyderabad Area, India

  • Responsible for cleaning some blocks with respect to Timing, IR, DRC, LVS and making the blocks ready for tapeout.

Soctronics

2 roles

Physical Design Engineer

Sep 2014Dec 2016 · 2 yrs 3 mos

  • Worked for AMD, at the client location in hyderabad.

Internship

Apr 2013Aug 2014 · 1 yr 4 mos

Krest

Implementation of 2-4 and 4-16 mixed logic line decoders

Sep 2011Feb 2012 · 5 mos · Hyderabad Area, India

  • Designing of 2-4 and 4-16 mixed logic line decoders.

Bharat heavy electricals limited

Electronics Engineering Intern

May 2011Aug 2011 · 3 mos · Hyderabad Area, India

Education

VEDA IIT

Master's degree — VLSI

Jan 2012Jan 2014

Jyothishmathi Institute of Technological Sciences

Bachelor's degree — electronics and communication engineering

Jan 2008Jan 2012

TRINITY JUNIOR COLLEGE

M.P.C

Jan 2006Jan 2008

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