Dec 2022 – May 2024 · 1 yr 5 mos

• Video Sub-System Verification:
• For 7+ years at Qualcomm, My significant contribution to various verification activities of Snapdragon VIDEO IP. My role included leading block-level and Low Power Verification teams, focusing on test planning trough coverage closure, and driving UPF-based simulations to ensure critical Video IP functionality.
• ▪ Led the Low Power Verification Team, focusing on UPF-based Power Aware Simulations for both RTL and netlists (DCNL and PDNL), ensuring robust retention, isolation, level shifter and power domain functionality.
• ▪ Established an SDF-enabled Gate Level Simulation Flow for precise timing simulations.
• ▪ Directed verification activities for critical IP blocks like the ‘In-Loop Filter Engine’ and ‘Film Grain Processing’, From test plan development through the coverage closure.
• ▪ Designed a versatile, switchable testbench that enabled parallel sub-block level verification and accelerated bring-up.
• ▪ Integrated advanced pre/post-processing algorithms, such as pixel-based image generation and stall-based verification, to optimize coverage closure.
• ▪ Leveraged Mentor InFact to automate functional coverage closure, which notably improved verification time.

Dec 2019 – Nov 2022 · 2 yrs 11 mos

Mar 2017 – Nov 2019 · 2 yrs 8 mos

May 2015 – Feb 2017 · 1 yr 9 mos · Bengaluru Area, India

• Worked on the Z-Rasterization and Tile Buffer backend 3D Graphics pipeline blocks.
• Developed the CBR UVM environment components with scoreboards and functional coverage. Modules are connected with four other neighbor modules, replicated neighboring module functionalities which will drive the data towards the RTL. The testbench supports configuration, scoreboards, bfms, monitors, checkers, assertions, coverage classes, debug interface, sequences, and sequence items.
• Plugged these benches to top-level GPU and GPS benches by enabling passive support.

Mar 2012 – Apr 2015 · 3 yrs 1 mo · Ahmedabad Area, India

• MIPI - Unified Protocol (UniPro) VIP:
• Implemented initial level test cases to verify basic architecture.
• List down all required features to be covered for all layers of UniPro and
• implemented it using covergroups and coverpoints along with DME fsm
• coverage.
• Help to implement Link configuration procedure and Link start-up
• procedure.
• Worked on developing tests and validating all scenarios for various Phy
• Procedures like Link Start-up, Link Configuration and Lane Hibernate
• Enter/Exit.
• MIPI – CSI2/DSI2/DPHY VIP:
• Enhancement of predefined max four lanes support to max eight lanes
• functionalities in the already developed CSI2/DSI2 VIP.
• Modified the error injection logic in ECC field which is not done previously in
• csi2 and dsi2 vip. Add error using exception features.
• MIPI RFFE VIP:
• Developed architecture for mipi-rffe vip and developed master and slave
• devices with the callbacks and functional coverage support.
• Defined packet class and virtual sequencer for multiple sequence generation.
• Developed Bus-Monitor which will easily plug and play on either side to check
• protocol correctness from the Bus traffic.
• Developed the VIP architecture which is totally managed from the
• configuration controller.
• NVMe VIP:
• Implementing a queue management stuff which will be used in both Host as
• well as Controller to simplify storage generation and management
• functionalities.
• Developed Physical Region Page (PRP) functionality which enables Host to
• smoothly access virtual memory through APIs.
• Developed transmitter and receiver functionality at Host side
• UniPro Switch:
• Developed the test bench environment and Verified UniPro Switch IP using
• SV during my onsite visit at Toshiba Electronics Europe GmbH, Germany.
• Achieved full code coverage by writting corner cases and also written exclude
• list for unreachable scenarios.