Milanpreet Kaur

Product Manager

Noida, Uttar Pradesh, India11 yrs 9 mos experience

Highly Stable

Key Highlights

12+ years of experience in ML/AI infrastructure.
Expert in building scalable distributed systems.
Proven track record in performance optimization.

Stackforce AI infers this person is a highly skilled ML/AI Infrastructure Engineer specializing in EDA and Gaming sectors.

Contact

Skills

Core Skills

Systems DesignHigh Performance Computing (hpc)MlopsDistributed SystemsObject-oriented Programming (oop)Performance TuningC++Game DevelopmentLinuxEmbedded Systems

Other Skills

ConcurrencyC++17Field-Programmable Gate Arrays (FPGA)KubernetesAmazon Web Services (AWS)Microsoft AzureSoftware ObservabilityDockerMicroservicesTerraformPyTorchGPU resource optimizationData StructuresProfilingBDD Li

About

ML/AI Infrastructure Engineer working at the intersection of distributed systems and production AI platforms, building the infrastructure that other engineers depend on. With 12+ years across Intel, Cadence, and Mentor Graphics (Siemens EDA), I’ve built systems where performance, reliability, and scale are non-negotiable. I now apply that foundation to modern AI infrastructure: GPU platforms, MLOps pipelines, RAG systems, and LLM deployment. I focus on the hard problems behind production AI such as resource management, observability, reliability, and cost-performance, turning models into systems that actually run at scale. After August 2025, I took a deliberate break for health and used that time to go deep on modern AI tooling, building RAG pipelines, exploring LLM serving patterns, and staying close to emerging infrastructure challenges. Now looking for senior roles owning platform architecture and solving complex infrastructure problems end-to-end.

Experience

11 yrs 9 mos

Total Experience

1 yr 11 mos

Average Tenure

Current Experience

Cadence

Principal Software Engineer

May 2023 – Jul 2025 · 2 yrs 2 mos · Noida · Hybrid

Worked on backend architecture and performance optimization of a distributed compute platform used for large-scale hardware emulation workloads.
Focused on improving execution efficiency, observability, and reliability of multi-stage processing pipelines handling compute-intensive workloads.

ConcurrencyC++17Systems DesignField-Programmable Gate Arrays (FPGA)High Performance Computing (HPC)

Intel corporation

Team Lead

Apr 2021 – Mar 2023 · 1 yr 11 mos · Bengaluru · Hybrid

Delivered and scaled cloud-native GPU-enabled ML/AI infrastructure supporting internal EDA workflows.

MLOpsKubernetesAmazon Web Services (AWS)Microsoft AzureDistributed SystemsSoftware Observability+5

Mentor graphics

2 roles

Lead Member of Technical Staff

Nov 2017 – Apr 2021 · 3 yrs 5 mos

Object-Oriented Programming (OOP)LinuxData StructuresProfilingPerformance TuningBDD Li+2

Senior Member of Technical Staff

Nov 2017 – Nov 2019 · 2 yrs

Object-Oriented Programming (OOP)LinuxData StructuresC++Visual C++

Aristocrat

Engineer II

May 2016 – Oct 2017 · 1 yr 5 mos · Gurgaon, India · On-site

Game development
SIT Issue Debugging on Windows(Visual Studio 2015) & Linux
Coding in C++ in real-time environment to pull together complex mathematical routines, images, animations and sound files into a final game program.
Worked on MGL and Clone Casino Games.
Managed teams to drive various projects.
Mentored new Joinees during the Induction process

Object-Oriented Programming (OOP)LinuxData StructuresC++Visual C++

Aricent

Software Developer

Nov 2013 – Apr 2016 · 2 yrs 5 mos · Gurgaon, India

 Ownership of Flexi platform’s Layer Manager Component, developed SCLI based UI for network configuration, Alarm
mechanisms for fault detection, performance monitoring and reporting.
 Developed Python-based regression suite for Layer Manager Component, reducing release readiness time by 70%.
 Led end-to-end performance benchmarking for data packet processing by DPDK based Lite EPC Fastpath on Intel/Cavium processors.

Object-Oriented Programming (OOP)LinuxData StructuresC/C++11/14/STL/VC++Shell/ Python (ROBOT)Linux/Windows+4

Tt consultants – global ip firm

Patent Research Analyst Trainee

Jul 2012 – Dec 2012 · 5 mos · Chandigarh Area, India

Responsible for Patent reading and Technology analysis
Performed Prior Art searches, Patentability, Invalidation of patents, Clearance searches and Generating reports for Patents of Electronics and Semiconductors specialization of fortune 500 companies.

Cdac

Trainee- Embedded Systems Design

Jun 2011 – Jul 2011 · 1 mo · Mohali, India

Project: LCD Based Digital Alarm Clock
Role: Designed and coded the digital clock with time and alarm setting function.
Technology: Embedded C, Keil Software, AT89S51, Embedded System design.
Implemented on PCB board an 8051 Microcontroller based Digital alarm clock controlled by the clock pulse frequency generated using IC1 555 that worked in 12hour mode and displayed time digitally on 16*2 LCD display interfaced with Microcontroller.