Sudhish Pandey

Product Engineer

Noida, Uttar Pradesh, India16 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design for advanced technology nodes.
  • Proven track record in RTL-GDS2 solutions implementation.
  • Strong background in EDA tools and methodologies.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in EDA tools and methodologies.

Contact

Skills

Core Skills

Physical DesignSocSynthesisEda

Other Skills

FloorplanningClock Tree SynthesisPlacementRoutingRC ExtractionStatic Timing AnalysisDRCLVSConformal LECSignal IntegrityPower AnalysisPhysical VerificationPlace & RouteTCLVLSI

Experience

16 yrs 3 mos
Total Experience
2 yrs 7 mos
Average Tenure
7 yrs 3 mos
Current Experience

Wipro

2 roles

Physical Design Engineer

Mar 2019Present · 7 yrs 3 mos

FloorplanningClock Tree SynthesisPlacementRoutingRC ExtractionStatic Timing Analysis+18

Technical Lead

Mar 2019Present · 7 yrs 3 mos

Ust global

Sr. Physical Design Engineer

Mar 2017Feb 2019 · 1 yr 11 mos · Noida Area, India

Mentor graphics

RTL-GDS Product Specialist II

May 2014Apr 2017 · 2 yrs 11 mos · New Delhi Area, India

  • As an Individual Contributor have two facets of my role. Internally have to drive to resolve current issues in tool, externally have to manage product deployment at customer site.
  • Summary:
  • Experienced in implementation and deputation for complete RTL-GDS2 solutions using Oasys-RTL, Nitro, and Calibre
  • Physical Design:
  • Physical Design Enablement for 7nm technology node in full flow certification for TSMC
  • Physical Implementation of ARM cores A7/A9
  • Synthesis:
  • Development flows and drive RnD for product development and functionality
  • Product Marketing and Deployment across various customers for Oasys-RTL Synthesis and Nitro PnR tools
  • In-Charge of the low power portfolio. Takes care of multi-voltage aspects of Synthesis flow
  • Integration between Synthesis & PD of low power designs in complete RTL-GDS flows
Oasys-RTLNitroCalibrePhysical Design EnablementPhysical ImplementationSynthesis+5

Nvidia

IC-Physical Design Consultant

Nov 2012Nov 2013 · 1 yr · Bangalore

  • Working with Global team to implement next generation GPU's & Tablets

Smart play technologies

Associate Physical Design Engineer

May 2011Apr 2014 · 2 yrs 11 mos · Bengaluru Area, India

  • Worked on 180/130/65/40/28 nm Tech Nodes
  • Floor-Plan, Power Planning, Placement and Routing, Static Timing Analysis, Clock Tree Synthesis, In-Place Optimization, Cross talk Analysis, IR Drop Analysis and Physical Verification
  • EDA Tools :
  • SOC Encounter,Aprisa : Floor plan, Place and Route, CTS
  • QRC : RC-Extraction
  • ETS : Signal Integrity & Timing Analysis
  • CALIBRE : DRC/LVS
  • CONFORMAL: LEC
  • POWER METER : Power Analysis
  • GOLDTIME : Static Timing Analysis
Floor-PlanPower PlanningPlacement and RoutingStatic Timing AnalysisClock Tree SynthesisIn-Place Optimization+13

Pmc-sierra

IC-Physical Design Consultant

May 2011Jul 2012 · 1 yr 2 mos · Bangalore

Silicon world

Technical Advisor

Aug 2009Dec 2010 · 1 yr 4 mos · New Delhi Area, India

  • Development of Robots used for Education

Education

College of Enguneering Roorkee

B-Tech — Electronics & Telecommunications

Jan 2005Jan 2009

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