V

VENKAT RAJKUMAR BOMMADENI

Product Manager

Bengaluru, Karnataka, India13 yrs 6 mos experience

Key Highlights

  • 15+ years in ASIC Physical Design leadership.
  • Expertise in RTL-to-GDSII closure across multiple technologies.
  • Successfully taped-out 7 network router chips.
Stackforce AI infers this person is a Semiconductor Physical Design expert with extensive experience in ASIC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignAsic

Other Skills

Place & RouteTechnical Project LeadershipHigh-speed Digital DesignPeople ManagementDRCPhysical VerificationTCLLVSCadence VirtuosoStatic Timing AnalysisTiming ClosurePerlShell ScriptingVHDLPrimetime

About

- 15+ Years of work experience in the ASIC Physical Design (PD) and executed different roles from individual contributor, lead and manager roles (both technical and managerial). - Current roles and responsibilities are led team from Physical Design front and execute from RTL-to-GDSII closure (involving Synthesis, Floorplan, Placement, CTS(Clock Tree Synthesis), Routing, Static Timing Analysis(STA), Addressing the IR Drop and EM issues and Physical Verification(DRC, LVS, Antenna and DFM checks)). - Have a good understanding at PD front on GPU, APU, Mobile Processor Chips, Automotive Chips, Network router switches and Network application chips in 45nm/32nm/28nm/20nm/16nm/11nm/8nm/7nm/5nm/4nm TSMC/Samsung technology nodes. - Proficient knowledge in scripting in TCL, PERL and Shell. Expertise in EDA tools: Synopsys - FC Compiler, IC Compiler, IC Compiler2, Prime Time-SI, IC Validator, IC Validator Cadence - Encounter, Innovus Mentor - Calibre, CalibreDRV Layout Editor Apache - Redhawk

Experience

13 yrs 6 mos
Total Experience
--
Average Tenure
--
Current Experience

Qualcomm

3 roles

Senior Staff Engineer

Jun 2024 – Present · 2 yrs · Bengaluru · On-site

Place & RouteTechnical Project LeadershipPhysical DesignASIC

Staff Engineer/Manager

Promoted

Dec 2019 – Apr 2022 · 2 yrs 4 mos

  • I worked in Tiles and Peripherals (T&P) BDC Team and played the Lead & Manager role (as Technical and People Manager).
  • Responsible to take all the T&P blocks from netlist to GDSII in a project and deliver it with tape-out quality.
  • T&P blocks are challenges with LowPower design ( like various PowerDomains AON/ON-OFF/Multi-Voltage/etc.,) and these blocks are carries huge amount of FeedThrough ports and custom buffer additions to meet the soc level requirements and weird block shapes.
Physical DesignASIC

Sr. Lead Engineer

Aug 2017 – Dec 2019 · 2 yrs 4 mos

Physical DesignASIC

Intel corporation

Silicon Design Engineering Manager (Physical Design)

Apr 2022 – May 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India

  • - Worked for Intel IFS (Intel Foundary Services) Team
Physical DesignASIC

Einfochips

Senior Physical Design Engineer (ASIC)

Nov 2012 – Aug 2017 · 4 yrs 9 mos · Ahmedabad

  • Worked with US Based product companies (like AVAGO (formally Broadcom) and ALTERA(it is Intel company)) on Network router Chip and Networking application chips in 28nm, 20nm & 16nm.
  • Worked as a Team lead and Individual contributor roles, to take the blocks from netlist to GDSII.
  • Successfully taped-out '7' Network router chips in 28nm/20nm/16nm.
Physical DesignASIC

Amd (consultant from soctronics, hyderabad, india)

Senior Physical Design Engineer

Dec 2008 – Oct 2012 · 3 yrs 10 mos · Hyderabad Area, India

  • Worked at AMD as a consultant for almost 4 years.
  • Held different positions like Engineer Trainee/Physical Designer/Sr. Physical Designer.
  • Roles played at Block Level as a Tile Lead and Individual Contributor role in Physical Design from Netlist to GDSII.
  • During my tenure, I recognized '3' times with Spot Recognition Awards(SRA) in different projects.
  • Participated in '4' full time projects and as well given support few other projects for a short period of time for project closure.
  • Worked on GPU & APU (Accelerated Processing Unit) projects.
  • I got an opportunity to worked on largest GPU/APU projects which are AMD's biggest chips in 28nm.
  • Exposure in several deep sub-micron technologies like 90nm/45nm/32nm/28nm/22nm.
  • Proficient knowledge in Timing & Physical Verification Closure.
  • Proficient skills in scripting like in TCL/PERL/shell.
Physical DesignASIC

Education

Osmania University, Hyderabad

Master of Science (M.Sc.) — Applied Electronics

Jan 2004 – Jan 2007

C-DAC (Centre for Development of Advanced Computing), Pune, INDIA

PG Diploma in VLSI Designing — VLSI

Jan 2008 – Jan 2008

Government Degree & PG College, Godavarikhani

Bachelor of Science (B.Sc.) — Computer Applications

Jan 2000 – Jan 2003

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