Sagar Dharmale — Software Engineer
1) Strong expertise in Low power standards (1801, UPF) static checks. Proficient in addressing Low power design implementation challenges through static checks (CLP/ VCLP) at RTL as well PD stages. 2) Power Estimation and optimization at synth as well as PD stages using PTPX.
Stackforce AI infers this person is a VLSI design expert with a focus on low power engineering.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Low-power Design
- Static Timing Analysis
Career Highlights
- Expert in low power design and static checks.
- Proficient in power estimation and optimization.
- Strong background in VLSI and digital IC design.
Work Experience
Qualcomm
Senior Lead Engineer (2 yrs 1 mo)
Engineer (1 yr 7 mos)
Silicon Engineer (1 yr 11 mos)
Eximius Design
Design Engineer (1 yr 4 mos)
Intel Corporation
Graduate Technical Intern (11 mos)
Education
Master of Technology - MTech at Vellore Institute of Technology
Bachelor of Engineering (BEng) at Pimpri Chinchwad Education Trust'S. Pimpri Chinchwad College Of Engineering
HSC at Jankidevi bajaj college of science wardha
