Dipak Vaghela

Director of Engineering

Bengaluru, Karnataka, India10 yrs 1 mo experience

Highly Stable

Key Highlights

Expert in Analog Layout design for advanced semiconductor technologies.
Hands-on experience with leading EDA tools like Cadence and Synopsys.
Proven track record in SRAM and memory compiler projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Analog Layout.

Contact

Skills

Core Skills

Analog LayoutVery-large-scale Integration (vlsi)

Other Skills

LPDDR ProjectTCL(Synopsys)SKILL(Cadence)Shell Scripting LanguageSRAMROMLevel ShifterSense AmplifierCurrent MirrorBand Gap BlocksVirtuoso (Cadence)IC Custom Compiler (Synopsys)5nm7nm7PLUSnm

About

Currently working at Faraday Tech as Analog Layout design Engineer

Experience

10 yrs 1 mo

Total Experience

4 yrs 4 mos

Average Tenure

1 yr 5 mos

Current Experience

Cadence

Lead Design Engineer

Jan 2025 – Present · 1 yr 5 mos · Bengaluru, Karnataka, India · Hybrid

Faraday tech

Senior Analog Layout Design Engineer

Jul 2019 – Jan 2025 · 5 yrs 6 mos · Bengaluru Area, India

Working on LPDDR Project
Basic Knowledge of TCL(Synopsys), SKILL(Cadence) and Shell Scripting Language.
Worked on SRAM, ROM, Level Shifter, Sense Amplifier, Current Mirror, Band Gap Blocks
Experience in Virtuoso (Cadence) and IC Custom Compiler (Synopsys) tools.
Experience in drawing leaf cell layout and top level integration for custom memory
Hands on experience on 5nm(TSMC),7nm(TSMC),7PLUSnm,12nm(TSMC),14nm(UMC), 16nm(TSMC), 28nm, 45nm and 180nm technologies.
Ability to draw area and route efficient layouts by adopting techniques such as transistor folding, well sharing etc.
Good ability to solve DRC, LVS for leaf cell and hierarchy layout
Good understanding of mask layers used to draw layout as per foundry document
Basic ability to solve EM, IR issue Good at concepts of VLSI and CMOS basics
Sound understanding of dual patterning in lower node technology
Good understanding of device matching techniques
Understanding of DFM rules
Familiar with SRAM architectures and functionality
Ability to adapt to the new technology
Quick learner on industry standard flows
Worked on Memory Compiler (SRAM)

LPDDR ProjectTCL(Synopsys)SKILL(Cadence)Shell Scripting LanguageSRAMROM+27

Synopsys inc

Layout Design Engineer

May 2016 – Jul 2019 · 3 yrs 2 mos · Hyderabad, Telangana, India

Worked on Memory Compiler (SRAM)
Experience in drawing leaf cell layout and top level integration for custom memory (SRAM)
Hands on experience on 5nm(TSMC),7nm(TSMC),7PLUSnm,12nm(TSMC),14nm(UMC), 16nm(TSMC), 28nm, 45nm and 180nm technologies.

Memory Compiler (SRAM)5nm7nm7PLUSnm12nm14nm+6