Anjali Makwana

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Key Highlights

Expert in Analog Layout and Verification.
Hands-on experience with leading semiconductor technologies.
Strong communication skills with design engineers.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog Layout and ASIC Design.

Contact

Skills

Core Skills

Analog LayoutLayout VerificationAsic Design

Other Skills

Custom CompilerCadence VirtuosoLayout Versus Schematic (LVS)Design Rule Checking (DRC)CalibreSynopsys IC CompilerSynopsys PrimetimeLinuxUCIeDTS IPDDRIOBGRPLSOPAMPsComparator

About

My goal is to excel in field of VLSI and work in learning and challenging environment, utilizing my skills, knowledge and contribute to personal growth as well as the organization.

Experience

3 yrs 11 mos

Total Experience

2 yrs 3 mos

Average Tenure

1 yr 8 mos

Current Experience

Synopsys inc

Senior Layout Design Engineer

Oct 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · Hybrid

Custom CompilerCadence VirtuosoAnalog LayoutLayout Versus Schematic (LVS)Design Rule Checking (DRC)Layout Verification+4

Intel corporation

Analog Layout Design Engineer

Jul 2022 – Oct 2024 · 2 yrs 3 mos · Bengaluru, Karnataka, India

Worked on projects like UCIe (Intel 18A & TSMC N6), DTS IP (Intel 1276) and DDRIO (Intel 1276).
Worked on critical blocks like BGR, PLS, OPAMPs, Comparator, LPF, etc.
Hands on experience in Floor planning, Power planning, Routing, Analog Matching Techniques, Shielding, etc.
Post layout verification: LVS, DRC and other verification checks.
Knowledge on Crosstalk, Latch-up, WPE, LOD, LLE, EM, Antenna violation and Matching.
Experience in handling ECO changes and also worked on reliability verification EM-IR checks.
Good communication skills to interact with design engineers to understand and build layouts as per requirements

UCIeDTS IPDDRIOBGRPLSOPAMPs+21

Rv-vlsi vlsi and embedded systems design center

ASIC Design Trainee

Dec 2021 – Jun 2022 · 6 mos · Bengaluru, Karnataka, India

Thoroughly understood the concepts of STA, Logic Design Concepts, CMOS, MOSFET, Semiconductor
Theory and Basic Electronic Devices.
Gained knowledge of ASIC Flow from Netlist to GDSII.
Acquired extensive knowledge and expertise in ASIC PD Flow involving Floor Planning, Power Planning, IR Drop Analysis, Automatic P&R, Clock Tree Synthesis and Routing.
Hands on experience in APR Tools - Synopsys ICC2 and STA Tools - PrimeTime.
Designed an ASIC Block in 40nm technology.

STALogic Design ConceptsCMOSMOSFETSemiconductor TheoryASIC Flow+7