Keshav Patil

Product Manager

Bengaluru, Karnataka, India9 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in low-power digital design and power estimation.
Led methodologies for Intel CPU and Client SoC projects.
Specialized in VLSI with a focus on next-generation transistors.

Stackforce AI infers this person is a Low Power Digital Design Engineer with expertise in VLSI and semiconductor industries.

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Skills

Core Skills

Low-power DesignPower AnalysisThermal AnalysisTimingFullchipVery-large-scale Integration (vlsi)

Other Skills

Power EstimationConvergenceCPUGPUSynopsis PrimePowerRTLEmulationInterconnect OptimizationInterconnect AnalysisInterconnects OptimizationQuantum MechanicsTransistorsSynopsis KelvinAutomation EngineeringSynopsys Primetime

Experience

9 yrs 10 mos

Total Experience

4 yrs 10 mos

Average Tenure

1 yr 2 mos

Current Experience

Google

Low Power Silicon Digital Design Engineer

Apr 2025 – Present · 1 yr 2 mos · Bengaluru · Hybrid

• Responsibile for power estimation and convegence for CPU, GPU compute IPs

Power EstimationConvergenceCPUGPULow-power DesignPower Analysis

Intel corporation

3 roles

Power/Thermal Estimation CAD & Methodology Engineer

Promoted

Jun 2021 – Mar 2025 · 3 yrs 9 mos

Led end-to-end power flows and methodologies for Intel CPU P-Core and Client SoC projects (BE - Synopsis PrimePower, RTL - Synopsis PrimePower RTL and Emulation - Synopsis EmPower/Wattson)
Led thermal flows and methodologies for Intel CPU P-Core projects (developed in-house as well as Synopsis Kelvin based solutions)

Thermal AnalysisPower EstimationSynopsis PrimePowerRTLEmulationPower Analysis

Fullchip Timing CAD & Methodology Engineer

Jun 2018 – Jun 2021 · 3 yrs

Led fullchip Interconnect and timing methodology for Intel P-Core projects
Developed multiple fullchip PPA optimization utilities and Interconnect optimization solutions

TimingFullchipInterconnect Optimization

Intern as Fullchip Interconnect Design Engineer

May 2017 – May 2018 · 1 yr

Worked on full chip global interconnect timing validation and optimization.

Interconnect AnalysisInterconnects Optimization

National institute of technology surat

Postgraduate Student

Jul 2016 – Jul 2018 · 2 yrs · Surat, Gujarat, India

Postgraduate with a specialization in VLSI and Embedded Systems. Worked on a project focused on designing next-generation transistors for advanced technology nodes, specifically the Single-Electron Transistor (SET), which operates on the principle of quantum tunneling between drain and source islands.

Quantum MechanicsTransistorsVery-Large-Scale Integration (VLSI)