Nandhini Balakrishnan

Product Manager

Limerick, Ireland7 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in processor architecture and SoC design.
Proficient in design verification and performance analysis.
Certified in Functional Safety Level 1.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in processor architecture and verification.

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Skills

Core Skills

Design IntegrationDesign Verification TestingPerformance Analysis

Other Skills

SystemVerilogPythonVerilogC (Programming Language)

About

Have good understanding of computer architecture mainly processor architecture. Experience in design and design verification of processor integration in an SoC, performance analysis of an SoC Certification in Function safety ( Level 1 )

Experience

7 yrs 4 mos

Total Experience

6 yrs

Average Tenure

1 yr 4 mos

Current Experience

Arm

Senior Engineer - Architecture Verification

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

Analog devices

2 roles

Design Engineer - Digital Design

Jun 2019 – Feb 2025 · 5 yrs 8 mos · Bengaluru, Karnataka, India

Performed design integration of ARM Cortex-M series micro controller.
Led verification efforts to build environment for verification and verified design integration of SHARC-FX core and ARM Cortex M33 microcontroller in ADSP - 2183x audio DSPs
Brought up the setup for directed testing of cores in embedded C language and wrote test vectors
Analysed performance ( in terms of latency and bandwidth analysis of interconnect) and also performed verification of initial booting sequence for ADSP - 2183x
Performed code and functional coverage analysis, wrote system verilog (SV) assertions/checkers/monitors and automated several tasks using python

Design integrationDesign Verification TestingPerformance AnalysisSystemVerilogPython

Student Intern

Jan 2019 – May 2019 · 4 mos · Bengaluru, Karnataka, India

Led the effort to automate the analysis of Memory Mapped Register (MMR) access latency by processors through system interconnect in ADSP - SC592 audio DSP SoC using system verilog (SV) monitors and python

SystemVerilogPython