Swarupa Kolli — Product Manager

19+ years of experience in Foundation IP library development and optimization, Library build, characterization, and physical verification activities. Currently I am working with Cadence as part of the IP group taking care of the quality aspects of the Analog and mixed signal Ips. As part of the Synopsys Solutions Group - IO Team, my responsibilities included full ownership of product quality and sign-offs, as well as improving processes and methodologies. I am also tasked with developing quality automation specifications. Additionally, I lead the Continuous Improvement Forum, conduct root cause analyses and implement preventive measures, and perform 8D analysis. I coordinate cross-functional activities and oversee the IP registration process with tier-1 foundries. I worked in the Synopsys Logic Libraries Build and Validation Team, where I was involved in qualifying digital IP libraries and managing IP QMS activities, including checklist analysis and customized RCA templates. I also worked at INVECAS, managing quality assurance for LOGIC, IO, analog, and complex IP. Involved in developing multiple libraries to meet various project needs such as speed, area, and leakage across 180nm to 90nm and 65nm technologies. Experience in standard cell GDS preparation, optimization, characterization, creating back-end views, benchmarking all libraries, and developing quality analysis flows. Leading the characterization of standard cell and IO libraries over an extensive PVT range based on project requirements using Synopsys Silicon Smart tools. •Comprehensive knowledge includes Data preparation, Floor planning, Power Planning, Placement, Clock tree synthesis and Routing activities Experience in cell/block level physical verification activities such as DRC, LVS. worked on physical verification product support. Worked on the tool migration to Cadence Suite. Successfully set up the characterization flow for standard cells, IOs including GPIO, USB, DDR, LVDS, crystal oscillatory pads, and different memory configurations. Established methodology and flow for generating and validating various back-end views such as LEF, VSTORM, Celtic, etc.

Stackforce AI infers this person is a VLSI and ASIC quality assurance expert with extensive experience in library development.

Location: Hyderabad, Telangana, India

Experience: 19 yrs 10 mos