Sharmila Venkata Subramanian

DevOps Engineer

Bengaluru, Karnataka, India8 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5+ years of experience in physical design engineering.
Expertise in deep submicron technology and design tapeout.
Proven track record of successful project ownership.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in advanced design methodologies.

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Skills

Core Skills

CtsPhysical Design

Other Skills

Design Rule Checking (DRC)ECO implementationPower distributionPerlCadence EncounterPPAPower OptimizationSynopsys toolsC++C (Programming Language)Static Timing AnalysisTiming ClosureUnixLinuxPhysical Verification

About

Physical Design & Application Engineer with 5+ years of experience in 5 full time successful projects from Floor Plan to Design Tapeout phase. Have worked on cutting edge 1.5GHz design projects in deep submicron technology. Strong expertise in physical design concepts: Floorplan, Placement, MSCTS, Routing, ECO implementation, clock and power distribution. Excellent communication skills exhibited during constant customer interactions. Have working knowledge in industry standard tools like ICC,ICC2, Fusion Compiler, Primetime. A pro-active, strong communicator with experience handling multiple high critical projects successfully.

Experience

8 yrs 5 mos

Total Experience

2 yrs 1 mo

Average Tenure

3 yrs 3 mos

Current Experience

Cadence design systems

Lead Design Engineer

Mar 2023 – Present · 3 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Synopsys inc

Senior Application Engineer

Sep 2021 – Mar 2023 · 1 yr 6 mos · Bengaluru, Karnataka, India

CTSDesign Rule Checking (DRC)

Soctronics

Physical Design Engineer

Jul 2018 – Sep 2021 · 3 yrs 2 mos · Greater Hyderabad Area

Worked on 5 full time projects starting from Floor Plan to Design Signoff phase for
the client with complete ownership of 3 blocks per project
Resolved a routing-critical block with 600k instance count by experimenting with
cell padding for AOI, OAI cells and using partial blockage, route guides in the
congested region.
Worked on ECO flow to implement all possible methods like skewing, adding
buffers, bypassing cells and sizing cells to clean the timing and Electricals.
Took additional responsibility by performing DRC, LVS and Antenna violations
cleaning.
Used the DFP (design for power introduction) techniques for power reduction with
power switches/gates inserting in the blocks.
Formed clustering regions for modules driving with Internal and external power and
controlled the power with power gaters ON/OFF mechanism.
Utilization issues were resolved by experimenting with placement blockage, split
blockages and partial blockages.