Manideep Attuluri

Product Engineer

Noida, Uttar Pradesh, India4 yrs 6 mos experience

Key Highlights

Expert in physical design for advanced technology nodes.
Proficient in power integrity and signoff tools.
Successful track record with major semiconductor clients.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and power integrity analysis.

Contact

Skills

Core Skills

Physical DesignPnrPower Integrity

Other Skills

synthesisplace and routesign-offfloorplanningplacementclock tree synthesisroutingtiming closurepower optimizationsignoff verificationpower analysisstaticIRdynamic IREM analysisICC2

About

Has been associated with 4 tape outs. Woked for different Clients i.e INTEL, RENASUS, NXP. Worked on PNR & signoff activities for lower nodes Have experience in fixing complex DRC's , antenna fixing, LVS ,and STA closure Have experience in closing complex blocks related to IR and EM violations Have experience in handling block and chip level designs belonging to 1.8nm, 5nm, 16nm, 28nm,45nm, 90nm Worked on SYNTHESIS, FLOORPLAN, PNR FLOW, STA AND SIGNOFF . Good hands on experience on Fusion complier, icc2, prime time (PT) redhawk ,redhawk sc, voltus.

Experience

4 yrs 6 mos

Total Experience

1 yr 1 mo

Average Tenure

Current Experience

Mirafra technologies

Senior Physical Design Engineer

Apr 2024 – Jul 2025 · 1 yr 3 mos · Noida, Uttar Pradesh, India · On-site

Worked as contractor to NXP Semiconductors' 16nm project, successfully designing and implementing 1 block. Key responsibilities included synthesis, place and route (PNR), and sign-off activities.

Physical DesignPNR

Keenheads

Design Engineer

Apr 2023 – Mar 2024 · 11 mos · Noida, Uttar Pradesh, India · On-site

Handled a block level partition at the 28nm technology node for the Renesas client, managing the complete physical design flow from synthesis to signoff. Responsibilities included floorplanning, placement, clock tree synthesis, routing, timing closure, power optimization, and signoff verification. Successfully delivered a clean block for tapeout by resolving IR/EM, DRC/LVS, and timing violations

Eximius design

ASIC Physical Design Engineer

May 2021 – Apr 2023 · 1 yr 11 mos · Bangalore Urban, Karnataka, India

Expertise in power analysis, staticIR, dynamic IR, and EM analysis (PGEM and SIGEM).
(Top and block level analysis)
proficient in the power integrity signoff tool - Redhawk (Ansys) and Redhawk seascape (RVSC) and Voltus and innovus