SHAIK THASHEEM PASHA

Product Engineer

Hyderabad, Telangana, India1 yr 6 mos experience

Key Highlights

Expert in RTL design and SoC integration.
Hands-on experience with Xilinx FPGA architectures.
Proficient in Verilog and VHDL for digital circuit design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and FPGA development.

Contact

Skills

Core Skills

Rtl DesignSoc IntegrationDsp DesignDigital Circuit Design

Other Skills

RTL CodingRTL VerificationAXISTADebuggingVivadoChipScopeDSP ArchitecturesXilinx FPGAsVHDLModelSimFPGASignal ProcessingPythonLanguage Skills

About

RTL / SoC Design Engineer with hands-on experience in micro-architecture specification, RTL design, and SoC-level integration. • Strong in Verilog, VHDL based RTL design • Experienced with AXI/APB/AHB protocols, CDC, and STA • Worked on high-speed DSP architectures (FIR, FFT, DDS) on Xilinx FPGAs • Hands-on with Vivado, ModelSim, ChipScope, and timing closure Currently seeking RTL / FPGA / ASIC Design opportunities.

Experience

1 yr 6 mos

Total Experience

1 yr 6 mos

Average Tenure

Current Experience

Unistring tech solutions pvt. ltd. (uts)

2 roles

SOC Engineer(RTL Design)

Promoted

Jul 2024 – Jan 2026 · 1 yr 6 mos · Hyderabad, Telangana, India · On-site

Defined micro-architecture specifications and implemented RTL modules meeting timing constraints
Designed and verified RTL for DSP blocks (FIR, FFT, DDS) on Xilinx 7-Series and UltraScale+
Performed SoC-level integration and verified AXI transactions between PS and PL
Achieved timing closure using STA by optimizing critical paths
Debugged hardware issues using Vivado ChipScope and logic analyzers

RTL CodingRTL VerificationAXISTADebuggingVivado+3

SOC ENGINEER

Jan 2024 – Jun 2024 · 5 mos · Hyderabad, Telangana, India · On-site

Designed and simulated digital circuits using VHDL for FPGA-based signal-processing applications. Worked with Vivado and ModelSim for testing and debugging.

RTL CodingVHDLVivadoModelSimDigital Circuit Design