Kumar Nandan — Product Engineer

As a Senior Principal Design Engineer at Cadence with extensive experience in PCIe/CXL controller development, and contribute to IP architecture, RTL development including Lint, CDC and Synthesis processes. With over a decade of experience in SoC design and implementation, my work is driven by a commitment to technical excellence and collaboration. My expertise encompasses front-end design, RTL integration, constraints modifications, and synthesis flows, enabling me to support cross-functional teams and projects effectively. Expertise : [ 2012-2025] ✅ RTL integration, PCIe + Ethernet lead. ✅ Hands on knowledge in Fusion Synthesis, RM FC Flow development. ✅ SOC Integration, Constraints, RTL Quality, FEBE Tech Lead. ✅ FE Implementation checklist Signoff lead. ✅ Synopsys design flow : VCS, Formality, Spyglass Lint, SDC and CDC. ✅ Hands-on experience on PT constraints consistency (PTC) and STA reports evaluation. ✅ Proficient in LINT, RDC, CDC, timing checks, FC sanity checks evaluation ✅ Supported customer engagements by providing technical expertise + addressing design query. ✅ Ability to work effectively in cross-functional teams and communicate technical concepts clearly. ✅ CoE Technical Lead [5yr] & Managed Tech-Mahindra, Mirafra, Sevitek. [2012 - 2025] ✅ Synopsys : SS delivery for PCIE+Ethernet Projects. ✅ INTEL : Server, HBM, IP lead for PCIE Gen4/5/6. ✅ Qualcomm Snapdragon Chips ✅ Broadcom : Routers, TCAM ✅ SanDisk : NAND memory [Synopsys] ✅ RTL Integration, Constraints updates, Led PCIe + Ethernet activities ✅ Fusion Compiler Synthesis Setup & Leading Fusion Synthesis Flow. ✅ FE implementation processes. perform floor planning, timing constraints. Formality ✅ RM FC Flow design, timing closure for PCIe/Ethernet. [INTEL] ✅ RTL Integration lead for SOC projects ✅ Fusion compiler Synthesis flow/LEC/Caliber/STA) , CDC, Fishtail. ✅ RTL checks and flows to maintain the health of SOC Design to deliver BE Team for Synthesis. ✅ Expertise in delivering FE collaterals + Synthesis delivery ✅ DC/FC Fusion compiler Synthesis, Caliber, Fishtail. ✅ EFFM Emulation design flow, STA analysis [QCM, BRCM] ✅ PCIE verification wrt Server projects, Networking chips ✅ Design Implementation Synthesis - DC Synth, PCIe, Coverage and Emulation - PCIe Link up ✅ GLS, Vectors, Code/Functional coverage, SDF & Timing Debug. ✅ Super macro verification for Router projects in BROADCOM. ✅ BROADCOM : Functional, ESPCV verification for TCAM, SCAN. Education: ✅CDAC RND VLSI design Pune :95.99%tile, AIR 21 ✅B.E in ECE : LNCT- 82.96% 1st rank in RGPV, Bhopal. Passion about Photography ~7yrs

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in RTL design and SoC implementation.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 10 mos

Skills

Rtl Design
Synthesis

Career Highlights

Over a decade of experience in SoC design.
Led multiple successful PCIe and Ethernet projects.
Expert in RTL integration and synthesis processes.

Work Experience

Cadence

Senior Principal Design Engineer (5 mos)

Synopsys Inc

Senior Staff Design Engineer, ASIC Design Implementation (1 yr 10 mos)

Intel Corporation

SOC Technical Lead (3 yrs 1 mo)

Senior Pre Si SoC Design Engineer (2 yrs 11 mos)

Qualcomm

Senior Engineer [ SOC Design Team ] (1 yr 3 mos)

Broadcom Inc.

Staff 1 Design Engineer (1 yr 11 mos)

Design Engineer 1 - IC Design (1 yr)

SanDisk

ASIC Design & Verification Engineer (1 yr 11 mos)

CDAC Centre for Development of Advanced Computing

VLSI Engineer at CDAC Acts PUNE, Got 95.99 percentile (6 mos)

Class Representative (5 mos)

PEC University of Technology, Chandigarh

Assitant Lecturer in Electronics department (1 mo)

LNCT Group of Colleges

Event Planner || Training and placement coordinator at LNCT (11 mos)

Education

P.G. in VLSI at Centre for Development of Advanced Computing (CDAC-ACTS) Pune HeadQuarter

Executive Management Development Program at Indian Institute of Management, Kozhikode

Bachelor of Engineering (B.E.) at Rajiv Gandhi Prodyogiki Vishwavidyalaya

Intermediate in Science at Ram Krishna (R.K.) College, Madhubani

Kumar Nandan

Product Engineer

Bengaluru, Karnataka, India14 yrs 10 mos experience

Highly Stable

Key Highlights

Over a decade of experience in SoC design.
Led multiple successful PCIe and Ethernet projects.
Expert in RTL integration and synthesis processes.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in RTL design and SoC implementation.

Contact

Skills

Core Skills

Rtl DesignSynthesis

Other Skills

PCIeCXLStatic Timing AnalysisPower AnalysisConstraint AnalysisASICTime ConstraintsTiming ClosureFusion synthesisFUSION COMPILERFront-End DesignCDCRDCTiming reports analysisClock domain crossing

About

Experience

14 yrs 10 mos

Total Experience

2 yrs 4 mos

Average Tenure

5 mos

Current Experience

Cadence

Senior Principal Design Engineer

Jan 2026 – Present · 5 mos · Greater Bengaluru Area · Hybrid

PCIe/CXL Controller Development : IP Architecture [ RTL Design, Synthesis ]
Working with AI teams and Improving AI Architecture for IP level Chip Design.
Expertise:
1. IP RTL design wrt PCIE controller, Lint , CDC, Genus Synth Flow
2. Conformal, ECO Flow , Equivalence Checking.
3. Logical and Physical synthesis
4. Static Timing Analysis
5. PPA analysis , Power Analysis
6. Constraint Analysis,
8. Design partitioning, Floor planning.
Working with Agentic AI Team to establish workflow and applying AI in IP RTL design + Synthesis at SSG.

PCIeCXLRTL designSynthesis

Synopsys inc

Senior Staff Design Engineer, ASIC Design Implementation

Mar 2024 – Jan 2026 · 1 yr 10 mos · Greater Bengaluru Area · Hybrid

Tech Lead role for PCIe + Ethernet Subsystem. [ Combo SS ]
✅ FE implementation of PCIE Gen 4/5/6 projects, worked in Ethernet Implementation.
✅ RTL-to-BE handoff, RM FC flow development, FC Synthesis execution lead
RTL FE Implementation lead, Timing SDC validation, NDM creation, Timing reports analysis, PTGCA closure.
Roles and Responsibilities at SNPS :
✅Responsible for FC synthesis, SS timing closure, clock domain crossing responsibilities.
✅RTL Integration, Constraints writing, Clock + Reset architecture design.
✅driving the life cycle of the Subsystem from TR phase, requirements to Release process.
✅Proficiency with Fusion compiler Synthesis, Formality flows development.
✅Signoff CDC, RDC , RM- FC synthesis.
✅Fusion Compiler FC Synthesis, NDM creation.
✅Development of RM FC Flow - Reference methodology flow
✅Hard IP ASIC views --> .LEF and .LIB creation, Formality - R2R and R2G Signoff
✅Timing closure for Subsystem level and Handled customer query wrt clock arch.
✅ Run PTGCA and well-versed with Synthesis and timing signoff processes for multiple SS handover to cust.
✅ Worked with FuSa Team and generated Area estimation reports for SS for PCIe Gen5/6 and Ethernet projects.
✅ Hands-on in timing closure using advanced timing analysis tools. PT signoff.

Constraint AnalysisRTL designSynthesisASICTime ConstraintsTiming Closure+6

Intel corporation

2 roles

SOC Technical Lead

Feb 2021 – Mar 2024 · 3 yrs 1 mo · Hybrid

A. SoC Design Lead in XSS [ 5 yrs ]
B. PCIE IP Design Implementation Lead [ 1.02 yrs ]
Manage group of 8 to 15 FE engineers, [ Hired Mirafra/Seviteck/Tech-Mahindra/Capegemini ] Employees and ramped up them wrt FE Implementation skills.
✅Recent 3 yrs Led Altran, Seviteck Semiconductor team guided and mentor many engineers/RCG for RTL.
✅Responsible for FE Synthesis, LEC, FEV, Fishtail.
✅Mentored 2 FE Interns in RTL Design till conversion FTE since 2k18 and provided guidance for RCG.
✅Hands on Experience in SOC Design and Implementation activities.
✅Deliver FE collaterals , Initial level Synthesis, done Equivalence checks - LEC, Syn2Sim checks.
✅Worked on setting up GUI indicator to show Quality checks for RTL health.
✅Supported in "timing constraints coding, timing closure, floor planning, placement, CTS, routing"
Emulation Design : June'19 - Apr'20 : ZEBU emulation flow and Validated FE collateral.
✅Courses Completed : Technical Leadership development program - 2021, 2k22
Achievements: [ Multiple 25+ recognitions 2018 to 2024 ]
✅These awards and appreciation for showing "results driven" and "One Intel" mindset as following :
1. for Enablement of FEBE Handoff drop in short span of time w/o cwf resource and handled Lint/CDC/Synthesis.
2. Timely Enablement for Handoff 2 Backend within short span of time.
3. for Excellence efforts in enabling H2B flow, Identified Automation needs, delivered to RTL collaterals to SD.
4. for working tirelessly and supported FEV task for RTL and FE 2 BE Syn2Sim closure , LEC closure and debug.
5. Paper presentation on DVT tool , learnt and guided to the Team for design tracing for faster debug.

RTL designSynthesisFormal Verificationpower awarefishtailpower estimate+2

Senior Pre Si SoC Design Engineer

Mar 2018 – Feb 2021 · 2 yrs 11 mos · Hybrid

Lead SOC Design Engineer at INTEL INDIA Headquarter at Bangalore.
✅Release PoC for PCIe IP, working on CDC, RDC flow setup.
PCIE Protocol, IPs RTL design experience. Worked on FC Synthesis, Setup of CDC + RDC Analysis.
Fusion compiler synthesis , Power Artist flow and FPV by using Jasper tool.
✅Hands on experience in RTL handoff to Structural Design/Physical Design Team.
✅SOC level/Block level Logic Synthesis,
✅DC Synthesis @SOC, FEV, Syn Caliber Signoff,
✅LEC Checks at SOC level [Logic Equivalence checks] , Signoff SYN2SIM checks.
✅Led Emulation EFFM activities at Intel Server Group, Xeon group @2019.
✅Worked with Chip model bring up Oregon team and supported new requests,
✅Experience in failure tracing, closure of SD feedback.
✅Worked closely with DFT+SD Team for SYN closure activities.
✅Done PCIe SS Verification, Denali VIP from Cadence.

RTL designSynthesisFUSION COMPILERCDCRDC

Qualcomm

Senior Engineer [ SOC Design Team ]

Dec 2016 – Mar 2018 · 1 yr 3 mos · Bengaluru · On-site

Summary : Worked with SOC Design Verification Team - MSM Team. [ Snapdragon Team]
✅Worked on Verification for Mobile SoC chipset, Qualcomm Snapdragon chips. [ 825 to 865 series]
✅ Worked on RTL for TLMM and padring coverage across SOC projects [ 825, 835 and 845 Series ]
✅ Responsible for TLMM block signoff.
✅ done VC formal for connectivity checking in Mobile SoC. CSV based approach
✅ SNUG paper for "Coverage improvement By using VC Formal" with Arun Prakash.
✅Part of SOC DV team Verifying Mobile chipset peripheral IPs.
✅Functional Design Verification, Formal Verification, SoC, GLS, PA GLS .
✅Code Coverage & Functional Coverage Development.
✅Worked on GLS, Vectors, ATE Vector generation.
✅Worked on assertions, VC Formal Tool.
✅Worked with SD team to generate GPIO Padring Level coverage. with SanDiego Team

Broadcom inc.

2 roles

Staff 1 Design Engineer

Jan 2015 – Dec 2016 · 1 yr 11 mos

✅worked directly with Arizona USA Team for Verification of COMBOPHY IP at Broadcom.
✅Mumbai - Broadcom [2yrs ] and Bangalore Broadcom : Jan 2016 to Dec 2016.
✅Directly reported to US team ( After Merging with Avago Tech )
✅ Worked as an Individual Contributor and successfully delivered SATA+ PCIe PHY Verification on time.
✅test plan creation, modification in UVM TB Environment , adding Sequences.
✅Owning SATA verification Module , PCIE Phy bring Up. Owning complete responsibility for SATA PHY.
✅Partial responsibility for PCIe PHY, done Code coverage by using VCS.
✅Code coverage and Functional coverages. done USB/sata/PCIe verification
✅ Worked on the complete ASIC cycle. ( in BRCM + Qualcomm )
Summary :
1. Functional Verification - Companies: SanDisk,Broadcom, Qualcomm,INTEL
2. Formal verification , Code + written cover points & bins for Functional Coverage
3. Power Aware verification- Qualcomm - GLS , PA GLS , delivered Vectors - US team
4. Supermacro verification , DFT and SCAN verification, Functional Coverage - Broadcom
5. NAND Memory design + Verification : SanDisk
6. SS Verification : PCIe Phy & controller Verification

Design Engineer 1 - IC Design

Jan 2014 – Jan 2015 · 1 yr

Responsible for all Verification activity :
✅ Functional Verification,
✅ ESPCV Verification,
✅ Logic Vision Verification,
✅ DFT -SCAN Verification.
Experienced area :
✅ Worked as a Chip Design & verification Engineer with the Knowledge Based Processor (KBP) Group.
✅ Worked in Code coverage , functional coverage writing, for KBP architectures.
✅ Worked in 2 Projects B2B : Test case development by using Verilog and SV.
✅ Done Scripting in PERL

Sandisk

ASIC Design & Verification Engineer

Feb 2012 – Jan 2014 · 1 yr 11 mos · Bengaluru Area, India · On-site

Got Job from CDAC Pune - during Placement Program from CDAC RND Pune.
✅ NAND memory flow development
✅ Verilog based IP Design and Verification.
✅Worked in NAND Flash + UFS(Universal Flash Storage)Projects.
✅MLM IP verification + Worked on clocks
✅ SVA & Formal Verification. Coverage - code + Functional , developed checkers
✅ AHB,I2C,APB.

Cdac centre for development of advanced computing

2 roles

VLSI Engineer at CDAC Acts PUNE, Got 95.99 percentile

Promoted

Aug 2011 – Feb 2012 · 6 mos

Selected post written and Technical Interviews with CDAC RND Team at Pune ACTS Headquarter.
✅ Got 95.99 percentile @July 2011.
✅CCPP - 1st day placed in CDAC Pune
✅Placed in SanDisk through Campus Placement Program on 1st day of Campus.
Aug 2011 – Feb 2012
✅Worked on class based verification environment using System Verilog.
✅Verified the RTL model using Verilog, Generated functional and code coverage.
✅Worked on Synthesis by using Xillinx tool.
✅done eSATA verification by using Verilog- responsible for Phy Layer.

Class Representative

Aug 2011 – Jan 2012 · 5 mos

Worked as a Class representative of D-VLSI batch with 18 members.
Responsible for class scheduling ,Companies coming for placement for VLSI batch. in CDAC Pune

Pec university of technology, chandigarh

Assitant Lecturer in Electronics department

Jun 2011 – Jul 2011 · 1 mo · Chandigarh

Faculty for Digital Electronics and Computer Architecture
Subjects :
1. Mobile Communication
2. Digital Electronics
Mentoring the young Engineers to grow in Electronics Domain..

Lnct group of colleges

Event Planner || Training and placement coordinator at LNCT

Jun 2010 – May 2011 · 11 mos · Madhya Pradesh, India

Worked as a Placement coordinator at LNCT with the supervision of "G P Mishra Sir"
worked along with "Divya Rathore Vagol"
link - https://www.linkedin.com/in/g-p-mishra-8565663/