Honey Garg

Product Engineer

Noida, Uttar Pradesh, India5 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Standard Cell Libraries and Characterization.
Proficient in IO validation and design of complex protocols.
Strong background in hardware design and firmware development.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC development and hardware design.

Contact

Skills

Core Skills

Asic Standard Cell LibrariesCharacterizationLibrary CharacterizationEda ToolsHardware DesignFirmware Development

Other Skills

CAD views GenerationDebuggingML Based Tool DeploymentData AnalysisPower AnalysisFunction ValidationEDA Tool ExplorationSchematic DesignSPI CommunicationSPI InterfaceStandard CellLow-power DesignRTL DesignVerilogEldo

About

Currently Working as Staff Engineer in IO Design Team - IP Group of Synopsys - where major work involves, schematic designing of GPIOs, mipi protocols like I3C etc and their complete validations Previously Worked as Design Engineer in Standard Cells IP Development Team - TDP Division of STMicroelectronics - where major work involves, Characterization and Different CAD views Generation of ASIC Standard Cell Libraries for various CMOS technologies.

Experience

5 yrs 5 mos

Total Experience

2 yrs 8 mos

Average Tenure

4 yrs

Current Experience

Synopsys inc

2 roles

Staff Engineer

Feb 2025 – Present · 1 yr 4 mos

Senior Engineer

Jun 2022 – Present · 4 yrs

till now, worked on
3X Rx Design
I3C Tx Design from scratch
Fail Safe Block Designing from scratch
Good Grip on Complete IO Validations i.e. timing, dc, soa, aging, power on sequencing, simultaneous switching noise etc.

Stmicroelectronics

3 roles

Design Engineer

Nov 2020 – Apr 2022 · 1 yr 5 mos · Greater Noida, Uttar Pradesh

Major Responsibility includes -
Characterization and Different CAD views Generation of ASIC Standard Cell Libraries, of various CMOS technologies.
Debugging of Cells form Design Point of View if issue comes during the process of Characterization.
Part of Deploying ML Based Tool in generating .lib data in production.
Different Data Analysis on the content of .lib
Worked on Setup Methodology of Flops.

CharacterizationCAD views GenerationDebuggingML Based Tool DeploymentData AnalysisASIC Standard Cell Libraries

Intern

Jun 2019 – Sep 2020 · 1 yr 3 mos · Greater Noida, Uttar Pradesh

Power – Performance – Area analysis of combinational cells. Constraint analysis: Setup, Hold, CP_Q delay of flops of different architecture.
Function Validation – Monte Carlo analysis, Cross Corner analysis. High Sigma Validation of flops of 28nm FDSOI technology using ELDO – FFP (Fast Fail Probability) tool.
Library Characterization and different EDA views generation for 28nm FDSOI and 40nm technology node.
EDA Tool Exploration: Exposure to Cadence – Virtuoso, ELDO, KRONOS. Exploring SOLIDO tool for ML Characterization to predict the .lib for PVT.
Working on designing of Ultra Low Power Standard cells for IoT applications in 40nm for M.Tech Thesis.

Power AnalysisFunction ValidationLibrary CharacterizationEDA Tool ExplorationEDA Tools

Intern

Jun 2014 – Dec 2014 · 6 mos · Greater Noida, Uttar Pradesh

Main Project: PLC Daughter Card for High Side Driver and Octal Terminator
Description: Based on VNI8200XP (octal high side smart solid state relay) for industrial I/O control, compatible with ST Nucleo and Arduino UNO boards. I did the Hardware Designing which includes schematic, layout and developed the Firmware to demonstrate the IC features, communicating over SPI protocol, developed on STM32 in IAR.
Minor Project: Automotive Grade LED Driver ALED1642GW: Evaluation Board
Description: In this project STM8 microcontroller is used to communicate with LED Driver over SPI Interface to demonstrate its all features. In this project I did the Firmware development, on STM8 in IAR.