SAURABH SINGH (सौरभ सिंह)

DevOps Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expertise in Memory Design and Characterization across multiple technology nodes.
  • Proven track record in PPA optimization and silicon debugging.
  • Strong background in low power and memory circuit design.
Stackforce AI infers this person is a Memory Design Engineer with expertise in semiconductor technology.

Contact

LinkedIn

Skills

Core Skills

Memory Design

Other Skills

CharacterizationBit-cell simulationsSenseAmp simulationsTiming AnalysisPPA OptimizationMonte-Carlo AnalysisMargin AnalysisTiming CharacterizationCircuit CheckStatic Timing AnalysisParasitic ExtractionVery-Large-Scale Integration (VLSI)ResearchCircuit DesignMicrosoft Office

About

Memory Design and Characterization Foundries : Samsung, UMC, GF , SMIC, TSMC Technology Nodes : 3/5/7/12/14/16/22/28 nm & 40 nm technology Interest area: Low Power Design, Memory circuit Design

Experience

7 yrs 9 mos
Total Experience
2 yrs 10 mos
Average Tenure
11 mos
Current Experience

Hcltech

Senior Technical Lead

Jul 2025 – Present · 11 mos · Hybrid

  • Memory Design and Characterization
Memory DesignCharacterization

Synopsys inc

3 roles

Staff R&D Engineer

Feb 2024 – Jul 2025 · 1 yr 5 mos

R&D Engineer Sr I

Jan 2024 – Feb 2024 · 1 mo

R&D Engineer II

Apr 2021 – Jan 2024 · 2 yrs 9 mos

  • Bit-cell and SenseAmp simulations and analysis.
  • Margining and characterization of compiler.
  • Write Assist Margin Analysis and improvement.
  • FullRC Timing Analysis.
  • PPA Optimization and design Updates.
  • Monte-Carlo Analysis for critical Margins.
  • Silicon issue Debug.
Bit-cell simulationsSenseAmp simulationsTiming AnalysisPPA OptimizationMonte-Carlo AnalysisMemory Design

Album semiconductors

Design Engineer

Jul 2018 – Mar 2021 · 2 yrs 8 mos · Bangalore

Arm

Memory Design Consultant

Jul 2018 – May 2020 · 1 yr 10 mos · Bangalore

  • Write and read Margin Analysis.
  • Timing and Leakage Characterization.
  • Circuit Check , ESPCV
  • Char Data validation.
Margin AnalysisTiming CharacterizationCircuit CheckMemory Design

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Dr. A.P.J. Abdul Kalam Technical University

Bachelor of Technology - BTech

Stackforce found 100+ more professionals with Memory Design

Explore similar profiles based on matching skills and experience

CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
CP

Chandramohan P

ASIC Physical Design, Staff Engineer

at Synopsys Inc

India18 yrs 8 mos exp
Physical DesignASIC SynthesisASIC Physical DesignAnalog Circuit Design
Venkiteswaran P N

Venkiteswaran P N

Associate

at PwC India

Hyderabad, India1 yr 9 mos exp
Data MigrationSAP HANA
Ravindra Shrivastava

Ravindra Shrivastava

Application Engineering

at Synopsys Inc

Acton, United States24 yrs 7 mos exp
Application EngineeringEmbedded Memory Design
SP

Sandeep Prabhakaran

Verification Engineer

at NVIDIA

Sunnyvale, United States2 yrs exp
Verification and Validation (V&V)UVM
Dheeraj Kumar

Dheeraj Kumar

Sr. Application engineer - PCIE VIP

at Synopsys Inc

Sunnyvale, United States3 yrs 11 mos exp
Universal Verification Methodology (UVM)PCIE ProtocolDesign VerificationVLSI VerificationSystemVerilog
Bhaskar Malyala

Bhaskar Malyala

Senior Hardware Design Engineer

at Intel Corporation

Bengaluru, India14 yrs 9 mos exp
Hardware Board DesignSignal IntegrityFirmware
Vinay C Shaju

Vinay C Shaju

Advanced Embedded Engineer

at Honeywell

Kerala, India5 yrs exp
DebuggingComputer Science
SAURABH SINGH (सौरभ सिंह) - DevOps Engineer | Stackforce