Indhu Kalaga — Product Engineer
Hi all, I am Indhu.I have recently completed my BTech from JNTU-GV. Aspiring Design Verification Engineer with strong fundamentals in Digital Electronics and hands-on experience in Verilog, SystemVerilog and UVM. Good understanding of UVM components such as driver, monitor, sequencer, agent, environment and scoreboard. Familiar with functional coverage, assertions and protocol basics like UART and APB. Currently seeking opportunities in VLSI Design Verification where I can apply my verification skills and continue learning advanced verification methodologies. Technical Skills: • Verilog • SystemVerilog • UVM • Digital Electronics • Functional Coverage • Assertions (SVA) • Protocol basics (UART, APB) Actively preparing for Design Verification Engineer roles.
Stackforce AI infers this person is a VLSI Design Verification Engineer with a focus on digital electronics and verification methodologies.
Location: Vizianagaram, Andhra Pradesh, India
Experience: 1 yr 4 mos
Skills
- Verilog
- Systemverilog
- Uvm
Career Highlights
- Strong fundamentals in Digital Electronics.
- Hands-on experience with Verilog and SystemVerilog.
- Aspiring Design Verification Engineer seeking growth.
Work Experience
QualSoC Technological Pvt Ltd
Design Verification Intern (1 mo)
Premier Energies Limited
Graduate Engineering Trainee (2 mos)
Maven Silicon
Design and verification internship (1 mo)
Design and verification Trainee (1 yr 1 mo)
SkillDzire
VLSI (1 mo)
SkillForge
Cyber security (1 mo)
IEEE
IEEE Student branch Treasury (1 yr 2 mos)
Silicon info systems
Hardware and networking /CCNA/MCSE/DCA (4 mos)
Education
Bachelor of Engineering at University College of Engineering, Vizianagaram
Diploma of Education at Andhra polytechnic college kakinada
1st-10th class at Siddhardha high school
