Neeraj I.

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in UVM methodologies for design verification.
Proven track record in NAND flash protocol verification.
Strong collaborative skills with design and implementation teams.

Stackforce AI infers this person is a Semiconductor Verification Engineer specializing in UVM methodologies and NAND flash protocols.

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Skills

Core Skills

Universal Verification Methodology (uvm)Test PlanningNand FlashUvm

Other Skills

Formal DVSemiconductorsRegression ManagementVS codeAMBA AHBAXIIP VerificationHardware VerificationAMIQ DVT eclipseCommunicationDigital DesignsCoverage AnalysisCode CoveragePerlNCSim

About

Mine work involves set up test benches and implement verification plans using UVM methodologies, ensuring that new RTL design features meet the highest standards of functionality and correctness. My education from NIT Trichirappalli in VLSI Systems underpins my approach to pre-silicon verification and collaborative problem-solving with design and implementation teams.

Experience

4 yrs 11 mos

Total Experience

3 yrs 7 mos

Average Tenure

1 yr 4 mos

Current Experience

Analog devices

Senior Design Verification Engineer

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

1)Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV
2)Architect the testbench and develop the verification environment in UVM and Formal based verification approaches
3)Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects
3)Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution
4)Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of DV evaluation
5)Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
6)Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team

Universal Verification Methodology (UVM)Test Planning

Western digital

2 roles

Senior Design Verification Engineer

Jul 2021 – Feb 2025 · 3 yrs 7 mos · Bengaluru, Karnataka, India

1)Test bench setup for SCA (separate command address) NAND flash protocol .
2)Worked on the Pre silicon verification of NAND flash Command sequence using UVM
methodologies.
3)Creation of verification plan for new RTL design feature and its implementation in UVM test bench
environment.
4)Conducted simulations and debugged failures to ensure design functionality and correctness.
5)Collaborated with design and implementation teams to identify and resolve design issues.
6)Weekly regression management along with failure analysis, failure debugs.
7)Initial Test bench setup while moving to new project- involves updating various test bench
component.
8)Worked on Jasper Gold connectivity App to validate connections in RTL design are as per design
intent.
9)Functional Coverage Analysis using cadence IMC.
10)Upgrading perl and python script for regression management and functional cover group
generation.
11) Collaboration with designers across 2 sites on design feature and bugs found .