ipshita sarkar — Software Engineer
Experienced Design Engineer . Skilled in Verilog, System Verilog, UVM, Digital Circuit Design,. Strong professional with a Master of Science - MS in Integrated Circuit Design from Technical University of Munich. Started Blogging regarding simple concepts of IC Design. Feel free to read from given link below- https://icdesignconcept.blogspot.com/
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and verification.
Location: Noida, Uttar Pradesh, India
Experience: 5 yrs 4 mos
Skills
- Rtl Design
- Verification
- Soc Verification
Career Highlights
- Expertise in RTL Design and Verification.
- Strong background in USB3/USB4 technology.
- Prolific blogger on IC Design concepts.
Work Experience
Synopsys Inc
Asic Digital Design Staff Engineer (1 yr 6 mos)
ASIC Digital Design Engineer- Sr Engineer (1 yr 5 mos)
FTDI Chip
IC Design Engineer (2 yrs)
Infineon Technologies
Intern (9 mos)
Space Applications Centre, ISRO
Project Trainee (5 mos)
Mentor Graphics
Internship Trainee (2 mos)
Education
Master of Science - MS at Nanyang Technological University Singapore
Master of Science - MS at Technical University of Munich
Bachelor of Technology - BTech at Manipal University Jaipur