Karan Tiwari — Software Engineer
👉 Passionate about learning the complex & at the same time interesting concepts lying behind the manufacturing of a semiconductor device in VLSI industry. 👉Currently positioned as a Design Verification Intern @ Cadence Design Systems. 👉Proficient in: ✨ UCIe IP Feature Verification ✨ Verilog delivery Testbenches ✨ DUT-VIP, DUT- DUT UVM Testbenches ✨ Functional & Code Coverage Analysis ✨ Register Verification. ✨ Creating BFMs, Sequences & Testcases. ✨ Scripting ✨ AMBA APB,AHB,AXI 👉Glimpse of my Technical Skills: ✨Digital Designing ✨Verilog ✨System Verilog ✨OOPs ✨SVA ✨UVM ✨Pearl ✨Linux
Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on VLSI design.
Location: Kanpur, Uttar Pradesh, India
Experience: 1 yr 10 mos
Skills
- Ucie Verification Ip
- Ucie
- Axi
- Functional Verification
Career Highlights
- Proficient in UCIe IP Feature Verification.
- Hands-on experience with Verilog and System Verilog.
- Strong foundation in VLSI design and verification.
Work Experience
Siemens Digital Industries Software
Senior Member of Technical Staff (1 yr 6 mos)
Member of Technical Staff (4 mos)
Cadence Design Systems
Design Verification Intern (11 mos)
Design Verification Trainee (1 mo)
Vodafone Idea Limited
GET (3 mos)
Hindustan Aeronautics Limited
Trainee (1 mo)
Education
Bachelor of Technology at Chhatrapati Shahu Ji Maharaj University
Intermediate at Army Public School (APS)
Highschool at Army Public School (APS)
