Oct 2019 – Apr 2021 · 1 yr 6 mos

• Migrate from SystemC based SOC verification environment to SV-UVM.
• Enhance and Integrate all the TB components such as UVCs and related sequences and tests for those blocks handled.
• Go through the evolving specifications and identify the scenarios to be tested and accordingly capture in Test Plan.
• Write Assertions for connectivity checks and low power scenarios and define coverage.
• Analyze coverage report and accordingly update the tests/testbench to reach 100% coverage.
• Scripting using Python.
• Concurrent Engineering.
• Power Aware simulation of MultiVoltage and Multiple Powedomain Power Management Block.
• Provide technical assistance to juniors in team and help them to achieve the goals.

Apr 2019 – Sep 2019 · 5 mos

• Write SystemVerilog Assertions to check Various signals in the SOC during low power scenarios - Formal Verification activity using SVA.

Sep 2017 – Mar 2019 · 1 yr 6 mos

• Involved in development of GLS testbench setup for boot up partitions such as power management unit, cache coherency unit and DDRPHY block GLS simulation.
• Complete Power aware GLS setup creation.
• Responsible for running Gate level simulation and related testcase failure debug.
• Debug all the failing scenarios and found many issues in the setup, standard cell libraries and in netlist.
• Closely working with Team and provide technical assistance and mentor juniors.

Feb 2017 – Sep 2017 · 7 mos

• WIFI subsystem verification, role is to verify all the registers in the design using UVM-RAL model.Verify the timeout block used to detect AHB bus hang- write sequence, test, and other UVM components to accomplish this. Do gate level simulation(GLS), Power aware gate level simulation (PAGLS) using UPF.
• language used:- C, system verilog. Methodology used is UVM. Tool used is VCS. Version control tool used is Perforce.

Oct 2015 – Feb 2017 · 1 yr 4 mos

• WIFI subsystem verification, role is to verify all the registers in the design using UVM-RAL model, Do gate level simulation(GLS), Power aware gate level simulation (PAGLS) using UPF.
• language used:- C, system verilog. Methodology used is UVM. Tool used is VCS. Version control tool used is Perforce.

Mar 2015 – Sep 2015 · 6 mos

• Hands on Experience To develop and Manage Coffee Plantation

Dec 2013 – Feb 2015 · 1 yr 2 mos

• career gap for competitive exams

Aug 2012 – Nov 2013 · 1 yr 3 mos · Bengaluru Area, India

• Soc verification of chip-set used in mobile phone:- Verified an arbiter used to communicate with the external PMIC which handles requests from various masters whose voltages can be varied. Did Boot rom code simulation in RTL by loading the code from the Software team into the memories in the chip and using correct fuses to boot the code from EMMC/SD/USB models. Wrote testcases of scenarios which will help in generating Power numbers of the chip-set at diffrent modes. Verified the peripherals module - SPI, I2C. Worked on toggle coverage closure. worked on integation of the peripheral VIP to generate the test pattern for I/O port characterization. Language used C, System verilog. Methodology used UVM. tool used Questasim, Verdi, denali model of memory devices.

Jul 2010 – Aug 2012 · 2 yrs 1 mo · Cochin Area, India

• Soc verification of Automotive safety critical MCU.
• Responsibilities are to verify the operation of the Cortex-R5 based chip in split-lock and Dual-core lock-step mode's. Verified the modules -Vectored interrupt manager(VIM), diffrent low power modes in SOC, verified pheripherals like SPI,I2C,UART, Inter processor communication module (IPC), watch dog timer, clock control module of the SOC, did Gate level simulation. language used C, Assembly and Verilog . tool used VCS
• SOC verification of MCU, Low power simulation using CPF, verificaiton of clock controller module, AHB bus matrix using System verilog assertions. Language used C, verilog. Tool used Ncsim.