Nour Daghlas — Software Engineer

As a VLSI Physical Digital Design Engineer, I specialize in designing high-quality chips with advanced EDA tools, including ICC2, DC-NXT, PT, Formality, Redhawk-SC, ICV. With years of experience at Synopsys' design services unit, I've been responsible for complete block ownership from RTL2GDSII that's DRC clean and timing closed. I'm also proficient in time management, communication, creativity, and attention to detail, which have helped me achieve design project milestones and estimate margins for last-second changes. What sets me apart is my ability to write top-notch tcl scripts for EDA tools, python/unix scripts to improve current design flows, meet custom requirements, and enhance debugging issues. My educational background includes a B.E. in Computer Systems Engineering from Birzeit University with distinction, where I graduated among the top 5% of my class with an 86.2% GPA. I'm highly motivated to pursue a career in digital physical design and create amazing chips with all the knowledge I've acquired in such a short time, and I'm committed to becoming a key member in achieving greater things. In addition to my hardware experience, I also have a solid background in programming and software engineering. As an experienced DevOps Engineer, I contributed to the success of Harri, a top-performing SaaS hospitality company recognized globally. I architected and built multi-Region solutions for eight main infrastructure services, migrated ten plus services of existing cloud infrastructure to Infrastructure-as-Code for AWS services, and achieved a 12% infrastructure reduction cost while maintaining performance to lower costs. If you're interested in connecting with me or learning more about my skills, please don't hesitate to reach out on LinkedIn or send me an email at NourDaghlas@gmail.com.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC implementation and EDA methodologies.

Location: Barcelona, Catalonia, Spain

Experience: 6 yrs 3 mos

Skills

Fusion Compiler
Asic Cad Flows
Physical Design
Digital Ic Design

Career Highlights

Expert in sub-5nm ASIC physical implementation.
Proficient in EDA tools and scripting for design optimization.
Strong leadership in managing complex VLSI projects.

Work Experience

Cisco

Senior ASIC CAD Engineer (11 mos)

Bridgz

VLSI Internship Supervisor (6 mos)

VLSI Backend Design Course Instructor (3 mos)

VLSI Backend Design Training Instructor (5 mos)

Synopsys Inc

Staff Engineer (1 yr 5 mos)

SoC Engineer Sr I (3 mos)

Physical Design Engineer - Contractor (1 yr 10 mos)

ASIC Design Consultant - Contractor (1 yr)

ASIC Design Consultant - Contractor (8 mos)

Aeliasoft

Physical Design Engineer (4 mos)

Birzeit University

Research And Teaching Assistant (3 mos)

Harri

DevOps Engineer (10 mos)

Education

Bachelor of Engineering - BE at Birzeit University

Bachelor of Engineering - BE at Università degli Studi di Parma

Nour Daghlas

Software Engineer

Barcelona, Catalonia, Spain6 yrs 3 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Expert in sub-5nm ASIC physical implementation.
Proficient in EDA tools and scripting for design optimization.
Strong leadership in managing complex VLSI projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC implementation and EDA methodologies.

Contact

Nourdaghlas@gmail.com LinkedIn

Skills

Core Skills

Fusion CompilerAsic Cad FlowsPhysical DesignDigital Ic Design

Other Skills

Application-Specific Integrated Circuits (ASIC)Place and routeStatic Timing AnalysisSignoffRTL2GDSIIPPAClock Tree SynthesisTCLEDA ToolsPython (Programming Language)Logic SynthesisTiming ClosureDesign Rule Checking (DRC)Physical VerificationLow-power Design

About

Experience

6 yrs 3 mos

Total Experience

1 yr 1 mo

Average Tenure

11 mos

Current Experience

Cisco

Senior ASIC CAD Engineer

Jul 2025 – Present · 11 mos · Barcelona, Catalonia, Spain · Hybrid

Senior ASIC CAD Engineer in Cisco's Silicon One organization, specializing in Synthesis, PnR, Signoff and STA for sub-5nm ASIC physical implementation with Synopsys Fusion Compiler. I develop and deploy CAD flows that help physical design (PD) teams meet timing closure, optimization, PPA targets, and signoff requirements for high-performance chips.
As primary flow owner, I support all PD engineers using Fusion Compiler, delivering stable, customizable methodologies and enabling smooth adoption of new tool features.
Key responsibilities:
Manage and refine end-to-end Fusion Compiler flows for sub-5nm (synthesis, PnR, optimization, STA/signoff) to ensure stability and PPA alignment.
Evaluate Synopsys Fusion Compiler updates through testing/validation; integrate validated enhancements with user-friendly, low-touch customization.
Provide technical support: debug issues, collaborate with PD/synthesis/verification teams, and advance methodologies for advanced nodes.
Key achievements:
Stabilized Fusion Compiler flows — reducing timing/DRC violations from unacceptable amounts to double-digit TNS/DRC levels and enabling PD team adoption of updated versions.
Built clock mesh synthesis flow from scratch in Fusion Compiler, supporting high-quality clocking across both PnR tools with tight skew and latency control.
Improved synthesis methodology: updated configs, removed outdated options, aligned with current tool capabilities — better QoR and fewer iterations.
Redesigned reporting for synthesis/implementation flows to enhance maintainability and debug efficiency.
Developed Python (AI-assisted) + TCL automation to optimize environment setup and flow operations.

Fusion CompilerApplication-Specific Integrated Circuits (ASIC)Place and routeStatic Timing AnalysisSignoffRTL2GDSII+19

Bridgz

3 roles

VLSI Internship Supervisor

Aug 2024 – Feb 2025 · 6 mos · Jerusalem · Remote

Lead and supervise internship for 5 interns after finishing VLSI training course with 23 students
Prepare ASIC design inputs and environment for the internship
Weekly followup with interns
Divide tasks for RTL2GDS flow for interns
Guide interns through VLSI concepts with practical experience on chip design

Very-Large-Scale Integration (VLSI)RTL2GDSII

VLSI Backend Design Course Instructor

May 2024 – Aug 2024 · 3 mos · Jerusalem · Remote

Conducted an instructor-led training that consists of 210 Hours of a comprehensive RTL2GDSII Design Course with theoretical, practical and hands-on full block backend implementation project for a group of 18 graduates in Electrical & Computer engineering B.Eng.

VLSI Backend Design Training Instructor

Oct 2023 – Mar 2024 · 5 mos · Remote

Conducted a training that consists of 210 Hours of a comprehensive RTL2GDSII Design Course with theoretical, practical and hands-on full block backend implementation project for a group of 18 fresh graduates in Electrical & Computer engineering B.Eng.

Project ManagementTechnical TrainingBackend Physical Design

Synopsys inc

5 roles

Staff Engineer

Promoted

Feb 2024 – Jul 2025 · 1 yr 5 mos

Implemented digital design of CPU and HSM blocks that comprised 3M+ cells for Tekton3 V2X Chip over a multi-tape-out project spanning 3 years.
Implemented digital design of CPU block that comprised >50% of chip area with 5M+ cells for Infineon's RC1 platform achieving a fully functioning first tape-out chip.

Engineering LeadershipEngineering Support

SoC Engineer Sr I

Nov 2023 – Feb 2024 · 3 mos

Physical Design Engineer - Contractor

Jan 2022 – Nov 2023 · 1 yr 10 mos

Develop test cases and documents for training in ICC2.
Full RTL2GDSII block ownership.
Floorplanning for 2 major blocks(2M+ Cells).
Power-Grid Development for multiple PG areas.
Implementing secure physical implementation techniques.
Timing-closure for high frequency block in 14nm process.
DRC Cleaning & sign-off for tape-out.

Analytic Problem SolvingSynopsys toolsPhysical DesignDigital IC DesignChipsetBackend Physical Design+8

ASIC Design Consultant - Contractor

Feb 2020 – Feb 2021 · 1 yr · Herzliyya, Tel Aviv, Israel

o Creating signoff quality methodology that automatically locates and fixes certain DRC errors such as Antenna, spacing & open/short violations for ICC2 tool detected by Calibre DRC results.
o Developing the Design Compiler, Formal Verification, Power Analysis & IR/EM Signoff flows for an automotive 22nm FD-SOI process for a tape-out quality IP.
o Developing solutions for issues related to TSMC Chip-Finish coloring techniques with Fusion Compiler.

Chipset

ASIC Design Consultant - Contractor

May 2019 – Jan 2020 · 8 mos · Herzliyya, Tel Aviv, Israel

Physical design training by Synopsys
ICC2/Fusion Compiler, DC, DC TOPO, DC NXT, Formality, PrimeTime PT training
Work on first physical design project with TowerJazz to close block from DRC perspective for critical Tapeout.

Chipset

Aeliasoft

Physical Design Engineer

Jul 2023 – Nov 2023 · 4 mos · Ramallah, West Bank · Hybrid

Place & RouteScripting

Birzeit university

Research And Teaching Assistant

Jul 2023 – Oct 2023 · 3 mos · Ramallah, West Bank · On-site

Developing VLSI Lab for a VLSI University course.
Assembling all required infrastructure & inputs to synthesize & implement a chip using educational cell libraries, tech files & other inputs for the P&R flow
Creating a full P&R flow RTL2GDSII
Writing lab manual for experiments to guide students and future teaching assistants to understand the inputs, the configuration and steps to run the backend chip design flow

System on a Chip (SoC)UnixInstructor-led Training

Harri

DevOps Engineer

Feb 2021 – Dec 2021 · 10 mos · Ramallah, West Bank

Cloud Solutions engineer
Terraform/Terragrunt IAC methodology development
AWS Multi-Region infrastructure
AWS Cost management and optimization
AWS VPC/Peering/SecurityGroups/Lambda/CloudFormation/CodePipeline/SNS/SQS/Athena/DMS/DataSync
AWS S3 Replication, Inventory, management and batch operations
AWS Cognito Applications
Boto3 library, AWS API scripting solutions

Python (Programming Language)