Kunal Jadhav

Product Engineer

Bengaluru, Karnataka, India9 yrs 1 mo experience

Highly Stable

Key Highlights

Expert in physical verification for photonics processes.
Proficient in CAD automation and PDK development.
Strong scripting skills in Python, Tcl, and Skill.

Stackforce AI infers this person is a Semiconductor and Photonics Engineering expert with a focus on CAD automation.

Contact

Skills

Core Skills

Physical VerificationCad AutomationPdk DevelopmentIpdk Solutions

Other Skills

Cadence VirtuosoCalibreCadence SkillSVRFPython (Programming Language)Tcl-TkDesign Rule Checking (DRC)Layout Versus Schematic (LVS)PERCPythonTCLAnalog Integrated Circuit DesignSilicon PhotonicsEngineeringVerilog

About

At Intel Corporation, we focus on advancing physical verification for photonics processes through innovative CAD flow setups and automation. With over a year of experience in curvilinear shape verification using Calibre DRC, our team ensures robust design and tapeout support. Collaborating with cross-functional teams, we maintain high-quality standards in QA automation to streamline workflows and optimize outcomes. Previously at Infineon Technologies, we contributed to the development of advanced PDK solutions, including SVRF rule decks, PERC rules, and physical verification support. Our expertise spans scripting in Python, Tcl, and Skill, enabling efficient CAD support and automation for diverse technology nodes. Passionate about enabling scalable and efficient design solutions, we aim to drive innovation in photonics and semiconductor design.

Experience

9 yrs 1 mo

Total Experience

2 yrs 4 mos

Average Tenure

2 yrs

Current Experience

Intel corporation

Electronic-Photonics Software Tools Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · Hybrid

Conducted physical verification using Calibre DRC for curvilinear shapes in photonics processes, ensuring high-quality design outputs.
Developed PDK Pcell components to enhance design flexibility and efficiency in semiconductor applications.
Provided design and tapeout support, facilitating seamless integration of physical verification into the CAD flow.

Cadence VirtuosoCalibreCadence SkillSVRFPython (Programming Language)Tcl-Tk+2

Infineon technologies

Staff CAD Engineer

May 2020 – Jun 2024 · 4 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

Played a key role in enhancing PDK requirements and verification processes at Infineon Technologies.
Developed Calibre SVRF Ruledeck and PERC rules, streamlining design workflows for efficiency.
Conducted rigorous PDK QA and Pcell development, ensuring high-quality tech files for integration.
Improved physical verification processes, resulting in increased design accuracy and reliability.

Cadence VirtuosoCalibreSVRFDesign Rule Checking (DRC)Layout Versus Schematic (LVS)PERC+4

Synopsys inc

2 roles

Application Engineer II

Nov 2018 – May 2020 · 1 yr 6 mos · Hyderabad, Telangana, India · On-site

Developed and implemented iPDK solutions using Python and TCL to enhance Custom Compiler Support.
Enabled advanced features such as Abutment, Stretch Handles, and Guard Rings, improving design efficiency.
Collaborated with cross-functional teams to optimize simulation processes, resulting in a reduction in simulation time.

PythonTCLiPDK Solutions

Technical Intern

Aug 2016 – Apr 2017 · 8 mos · Mumbai Area, India · On-site

Collaborated with the Quality Assurance Team at Synopsys Inc to enhance the reliability of Synopsys Avalon tool for VLSI testing.
Automated multiple applications using TCL, improving testing efficiency.
Conducted thorough testing and validation processes, ensuring high-quality software delivery.

Sankalp semiconductor pvt ltd

PDK/CAD Engineer

Apr 2017 – Oct 2018 · 1 yr 6 mos · Hubli Area, India · On-site

Led the development of primitive cells (nmos, pmos, resistors, capacitors) in Cadence Virtuoso using Skill language.
Successfully executed a project on MOS device development in Python with Synopsys Pycell Studio.
Performing QA for front-end components of PDK, enhancing reliability through rigorous batch simulations.
Contributed to CAD automation by scripting in Shell, Python, Skill, Perl, and Tcl, streamlining design processes.

Bhabha atomic research centre

Intern

Jul 2015 – May 2016 · 10 mos · Mumbai Area, India · On-site

Implemented the LwIP Protocol on a FPGA as part of my Master's Thesis at Bhabha Atomic Research Centre.
Developed a Time to Digital Converter module in Verilog, enhancing precision in data processing.
Configured an embedded microprocessor on FPGA using Embedded C, facilitating efficient communication protocols.
Created an HTML interface to monitor performance metrics, improving accessibility to data insights.