Abinaya V

Software Engineer

Bengaluru, Karnataka, India6 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in DFT with extensive experience in pre-silicon validation.
  • Proficient in ATPG and scan insertion techniques.
  • Strong background in semiconductor design and testing.
Stackforce AI infers this person is a DFT Engineer specializing in semiconductor validation and testing.

Contact

LinkedIn

Skills

Core Skills

PcieScan InsertionAtpg

Other Skills

Parallel GLSAutomatic Test Pattern Generation (ATPG)Mentor GraphicsMbistDFDBoundary ScanDigital ElectronicsAntennaElectromagnetic FieldsVlsiMicroprocessorsMicrocontrollersIthPythonSvSimulations

About

DFT ENGINEER(Pre-silicon and Post-silicon validation)

Experience

6 yrs 7 mos
Total Experience
1 yr 11 mos
Average Tenure
8 mos
Current Experience

Ibm

Hardware Engineer

Oct 2025 – Present · 8 mos · Bengaluru, Karnataka, India · Hybrid

PCIe

Tessolve

Senior Design Engineer

Mar 2025 – Sep 2025 · 6 mos · Chennai · On-site

  • Pre- silicon Validation| Scan Insertion | ATPG | GLS
Scan InsertionParallel GLSATPG

L&t technology services

2 roles

Senior DFT Engineer

Nov 2024 – Mar 2025 · 4 mos · Hybrid

Automatic Test Pattern Generation (ATPG)Mentor GraphicsATPG

DFT Engineer

Feb 2022 – Dec 2024 · 2 yrs 10 mos · Hybrid

  • DFT ENGINEER | VLSI DOMAIN | LTTS
Automatic Test Pattern Generation (ATPG)Scan InsertionATPG

Bosch global software technologies

Associate Engineer

Sep 2019 – Jan 2022 · 2 yrs 4 mos · Coimbatore, Tamil Nadu, India

Education

St. Joseph's Institute of Technology

Bachelor of Engineering - BE — Electronics and Communication Engineering

Jan 2015 – Jan 2019

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