Dheeraj Kumar — Software Engineer
As a design verification intern at Synopsys, I contribute to the development and testing of the PCIE VIP product, using UVM and SystemVerilog. I work with a team of experienced engineers to ensure the quality and functionality of the verification IP, and to resolve any issues or bugs that arise during the simulation process. I also apply my skills in RTL coding, and assertion based verification to support the design and verification of other products and projects. I have a master's degree in electrical and electronics engineering from Portland State University, where I gained a solid foundation in digital VLSI design, System verilog, Universal verification methodology(UVM) and OOP concepts. I also have three certifications from Maven Silicon in VLSI design methodology, system on chip design, and verification, which demonstrate my knowledge and proficiency in these domains. I am passionate about learning new technologies and tools in the VLSI field, and I aspire to become a successful and innovative engineer in this industry. Technical Proficiency: Programming Languages: Verilog, SystemVerilog Methodology: Universal Verification Methodology (UVM) Tools: Siemens-QuestaSim, Verdi, Xilinx-Vivado, GitHub, Per Force Operating Systems: Windows, Linux. Skills: UVM TB Architecture, constraint random verification (CRV), System verilog Assertions, OOP’s Protocols: Cache Coherence Protocols like MESI, ARM AMBA 3 AHB Lite, AHB, and APB. Computer Architecture: Memories (DDR), Cache, Pipelining, Branch prediction, MIPS.
Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in digital electronics and verification methodologies.
Location: Sunnyvale, California, United States
Experience: 3 yrs 11 mos
Skills
- Universal Verification Methodology (uvm)
- Pcie Protocol
- Design Verification
- Vlsi Verification
- Systemverilog
- Digital Design
- Verilog
- Rtl Design
Career Highlights
- Proficient in UVM and SystemVerilog for design verification.
- Hands-on experience with PCIE protocol and verification IP.
- Strong foundation in digital VLSI design and methodologies.
Work Experience
Synopsys Inc
Sr. Application engineer - PCIE VIP (1 yr 10 mos)
DV Intern - PCIE VIP (9 mos)
Qualcomm
Design verification intern (3 mos)
L&T Technology Services Limited
RTL Design Engineer (1 yr 1 mo)
Maven Silicon
VLSI VERIFICATION USING SYSTEMVERILOG (2 mos)
Truechip
SUMMER INTERSNSHIP (1 mo)
Maven Silicon
VLSI DESIGN METHODOLOGY USING VERILOG (1 mo)
Education
Master's degree at Portland State University
B.Tech at Manipal University Jaipur
intermediate at Narayana Junior College - India
SSC at Narayana concept school
