Jay Parekh

Software Engineer

Bengaluru, Karnataka, India9 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL design and verification methodologies.
  • Proven track record in ASIC digital design.
  • Hands-on experience with USB and IP development.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignVerilogIp Development

Other Skills

SystemVerilogChip ArchitectureHardware DesignCDCHardware Description LanguageLintDebuggingElectronicsDigital Circuit DesignVery-Large-Scale Integration (VLSI)Asic designMicrosoft OfficeMicrosoft WordPowerPointTeamwork

About

PROFESSIONAL ----Skills---- RTL design Lint CDC ----Languages----- Verilog ----Tools---- Mentorgraphics Questasim, CDC & Autocheck ----Concepts---- RTL Design RTL Coding USB PIPE APB AXI UART ----Scripting---- Shell HOBBIES DJ Singing

Experience

9 yrs 5 mos
Total Experience
2 yrs 4 mos
Average Tenure
4 yrs 11 mos
Current Experience

Synopsys inc

4 roles

ASIC Digital Design, Sr Staff Engineer

Promoted

May 2026 – Present · 1 mo

RTL DesignVerilog

ASIC Digital Design Staff Engineer

Feb 2024 – May 2026 · 2 yrs 3 mos

RTL DesignVerilog

ASIC Digital Design Engr Sr I

Promoted

Feb 2023 – Feb 2024 · 1 yr

SystemVerilogChip ArchitectureHardware DesignIP developmentCDCRTL Design+3

ASIC Digital Design Engr, II

Jul 2021 – Feb 2023 · 1 yr 7 mos

SystemVerilogIP development

Softnautics llp

Associate ASIC Engineer

May 2018 – Jul 2021 · 3 yrs 2 mos · India

  • Worked extensively on the Link Layer & PHY Layer of USB
  • Hands on knowledge of MIPI DSI, CSI2 and D-PHY
  • Responsibilities Included
  • Design and Lint/CDC Checks of
  • °Deskew
  • °Comma Detection
  • °Wrapper around color space converter
  • °AHB-Lite Master & Slave Implementation
  • °Packet Data Controller(Inhouse)
SystemVerilogIP development

Physical research laboratory

Engineering Project Trainee

Jan 2018 – May 2018 · 4 mos · Ahmedabad, Gujarat, India

Ieee ddu student branch

vice chair

Dec 2016 – Dec 2017 · 1 yr · Nadiād Area, India

Iit bombay

Intern

May 2016 – Jul 2016 · 2 mos · Mumbai

  • Made a Spherical Droid.

Education

Dharmsinh Desai University

Bachelor of Engineering (BE)

Jan 2014 – Jan 2018

Dharmsinh Desai University

Bachelor of Technology (B.Tech) — Electronics & Communication Engineering

Jan 2014 – Jan 2018

V J modi school

HSC — Science

Jan 2011 – Jan 2013

V. J. MODI SCHOOL

SSC — Secondary Education and Teaching

Jan 2009 – Jan 2011

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