Sangeeth S G — Software Engineer

I am a Senior Physical Design Engineer with 4+ years of hands-on experience in advanced-node ASIC Physical Design, including 3nm and 2nm technologies, specializing in block-level PnR, timing closure, and signoff for performance-critical SoC subsystems. I currently work with Qualcomm Physical Design teams in a contract role through a partner organization, contributing to advanced-node tapeout programs in a fast-paced, milestone-driven environment. I have successfully handled multiple block-level BTO and MTOs (5+ blocks), taking ownership from floorplanning through routing, timing closure, and ECO signoff. My experience includes working on high-density, congestion-sensitive designs with tight timing and power constraints, requiring close collaboration with STA, Frontend, DFT, and signoff teams. I am comfortable debugging complex timing issues, managing late-stage ECOs, and driving blocks to closure under aggressive PPA targets. I am keen to further grow in high-performance ASIC / SoC environments, including GPU, AI, Media, or compute-intensive subsystems, where advanced-node challenges, scalability, and design quality are critical.

Stackforce AI infers this person is a Senior ASIC Physical Design Engineer specializing in advanced-node technologies.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 6 mos