Jaskeerat Singh Mayall

Software Engineer

Delhi, India8 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in SERDES PHY design and implementation.
  • Strong background in FPGA prototyping and validation.
  • Proficient in multiple programming languages and design tools.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in digital design and FPGA prototyping.

Contact

LinkedIn

Skills

Core Skills

Digital DesignSerdes Phy DesignFpga DesignProduct Validation

Other Skills

RTL designFront end design implementationFPGA PrototypingEmulationC (Programming Language)Microsoft OfficePython (Programming Language)VerilogVHDLCadence VirtuosoDigital ElectronicsPSpiceMatlabComputer ArchitectureTeam Leadership

About

Currently working as a Sr Design Engineer at Qualcomm . Prior to this , I have worked in SERDES PHY design for 3 yrs at Synopsys and FPGA prototyping at Cadence Design Systems for 2.5 yrs. I have done Electronics and Communication Engineering from Delhi Technological University(Formerly DCE).

Experience

8 yrs 6 mos
Total Experience
2 yrs 8 mos
Average Tenure
5 mos
Current Experience

Qualcomm

Senior Engineer

Jan 2026 – Present · 5 mos

Synopsys inc

Sr Engineer Digital Design

Jan 2023 – Jan 2026 · 3 yrs

  • Worked in the PHY Design team for SERDES USB Type-C products (combining DP, USB3.x and USB4 modes)
  • RTL design and Front end design implementation for SERDES PHY
RTL designFront end design implementationDigital DesignSERDES PHY Design

Cadence design systems

2 roles

Intern

Feb 2021 – May 2021 · 3 mos

Product Validation Engineer I

Jan 2021 – Jan 2023 · 2 yrs

  • FPGA Prototyping & Emulation
FPGA PrototypingEmulationFPGA DesignProduct Validation

Enactus dtu

3 roles

Secretary General

Sep 2019 – Sep 2020 · 1 yr

Project head - Unnati

Aug 2018 – Sep 2019 · 1 yr 1 mo

Project member

Aug 2017 – Aug 2018 · 1 yr

Bharat electronics

Summer Intern

May 2019 – Jul 2019 · 2 mos · Ghazibad , U.P

Delhi metro rail corporation ltd

Summer Intern

Jun 2018 – Jul 2018 · 1 mo · New Delhi , India

Education

Delhi College of Engineering

Bachelor's degree — Electronics and Communications Engineering

May 2017 – May 2021

Delhi Technological University (Formerly DCE)

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2017 – Jan 2021

Amity University

PCM with Computer Science

Apr 2003 – Mar 2017

Stackforce found 100+ more professionals with Digital Design & Serdes Phy Design

Explore similar profiles based on matching skills and experience

RB

Rohan Bera

Sr. R&D Engineer

at Synopsys Inc

Portland, United States2 yrs exp
JavaScriptReact.jsPythonElasticsearchData Analytics
NM

Nitesh Mudgal

Research Scientist

at Bharat Electronics Limited

Bengaluru, India2 yrs 10 mos exp
AK

Ashutosh Kumar

Digital Design Engineer

at Analog Devices

Bengaluru, India2 yrs 7 mos exp
Digital IC DesignDesign integrationSTALow-power Design
CS

Chinnala Suvarna Raju

Physical Design trainee

at ChipEdge Technologies Pvt Ltd

Bengaluru, India3 yrs exp
ASIC Physical DesignSynopsys tools
BS

Bineet Srivastava

Director Software Engineering

at Cadence Design Systems

Noida, India25 yrs 8 mos exp
DD

Devashish Dhamat

Senior Research And Development Engineer

at Synopsys Inc

Bengaluru, India2 yrs 3 mos exp
Physical Design
AI

Anil Ingale

Design Engineer

at Tech Mahindra

Bengaluru, India3 yrs 9 mos exp
DFTEDAASIC
SP

Shrinklata Patel

Senior Engineer

at Qualcomm

Bhopal, India5 yrs 11 mos exp
Physical DesignStatic Timing AnalysisTiming Closure