Shrinklata Patel

Software Engineer

Bhopal, Madhya Pradesh, India5 yrs 11 mos experience

Highly Stable

Key Highlights

Experienced in Physical Design and Static Timing Analysis.
Proficient in multiple programming languages including C and C++.
Strong background in digital electronics and VLSI design.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisTiming Closure

Other Skills

TCLPlace & RouteDesign Rule Checking (DRC)InnovusFloor PlansVHDLVerilogDigital ElectronicsMicrosoft PowerPointC (Programming Language)C++Microsoft OfficeCadence Virtuoso

Experience

5 yrs 11 mos

Total Experience

5 yrs 11 mos

Average Tenure

5 yrs 11 mos

Current Experience

Qualcomm

3 roles

Senior Engineer

Promoted

Dec 2024 – Present · 1 yr 6 mos

Timing ClosureTCLStatic Timing AnalysisPlace & RouteDesign Rule Checking (DRC)Innovus+10

Hardware Engineer

Jun 2021 – Dec 2024 · 3 yrs 6 mos

Timing Closure

Interim Engineering Intern

Jul 2020 – Jun 2021 · 11 mos

Education

Maulana Azad National Institute of Technology

Master of Technology - MTech — Vlsi design and embedded system

Jan 2019 – Jan 2021

Jabalpur Engineering College

Bachelor of Engineering - BE — electronics and telecommunication

Jan 2013 – Jan 2017

Jawahar Navodaya Vidyalaya - JNV

12th

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