Sukesha Poojari

Design Manager

India14 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 15 years of experience in PDK/CDK engineering.
Expert in automation and validation for advanced tech nodes.
Proven track record in training and mentoring engineers.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in PDK/CDK development and automation.

Contact

Skills

Other Skills

CVLSIVerilogMixed SignalMatlabVerilog-AMSperfPerl AutomationCalibreSpectreODFMHerculesShell ScriptingCadence VirtuosoDebugging

About

"15+ Years of experience in PDK/CDK" • Experience on tech nodes 1.5nm,2nm,3nm,5nm,7nm,8nm,10nm,12nm,14nm,16nm,22nm,28nm, 40nm,45nm,50nm,55nm,65nm, 90nm,110nm,130nm, 180nm,350nm,450nm,750nm. • EMIR flow setup QA automation and customer support • Customer EMIR flow setup validation automations • Totem and Voltus complete EMIR deck validation by implementing automation including device and duty ratio coverage. • Developed PVS PERC rule deck including PAD,PERC gate area calculator,PERC domain based cap sum and full chip floating pin tracer. •oDFM,PVS,Assura,Hercules,Clibre,chameleon, K2 rule deck development for all foundry DM rules ,ERC and scribe seal rule decks and worked on porting of rule decks. •Worked on Wrapper pcell, Pcell updates, LAM file, • Setup , QA , flow support of PDK,DRC, LVS,QRC,VFI, EAD,EMIR,Assert • Worked on QC of pcells,regression,DRC,LVS,QRC,PERF,schematic simulations. • Developed Perl script for layout utility,Schematic Designs • Trained fresh engineers in rule deck development,TCL,perl,shell,skill,scripting and automation

Experience

14 yrs 10 mos

Total Experience

3 yrs 8 mos

Average Tenure

5 yrs 4 mos

Current Experience

Cadence design systems

4 roles

Sr Design Engineering Manager

Mar 2025 – Present · 1 yr 3 mos

Sr Principal Design Engineer

Jul 2024 – Apr 2025 · 9 mos

Principal Design Engineer

Promoted

Feb 2021 – Jul 2024 · 3 yrs 5 mos

Lead Design Engineer

Nov 2016 – Sep 2019 · 2 yrs 10 mos · Bangalore

PDK/CDK engineer

Globalfoundries

Principal Design Engineer

Sep 2019 – Feb 2021 · 1 yr 5 mos · Singapore

Karmic

PDK/CDK engineer

Aug 2011 – Nov 2016 · 5 yrs 3 mos · Manipal

5 year of experience in PDK/CDK
1)OpenDFM : oDFM rule deck development for 28nm,45nm,65nm,90nm tech nodes,Includes Basic,ERC,Additional,Miscellaneous and Scribe Seal design rules,inline PVS coding,porting of Hercules rule deck to oDFM deck,regression,TCL scripting,Verifying the rule deck on Full Chips,perl scripting to generate Excel Dashboard
>Cadence Virtuoso ::
2)CDB to OA conversion for 750nm tech node,creating QC cells,DRC&LVS fixes,QRC,schematic simulation,Basic PCELL correctness, Series Check, Parallel Check, Parameter Checks, Soft Connect Checks, Connectivity Checks,verifying the cells with PERF Validation,learning of Xpress tool.
3)PDK support for 180nm libraries with various flows,AMS,Spectre view creation for model verification,debugging,schematic verification,shell scripting,verifying the cells with PERF Validation,
Excel Dashboard creation
4)Assura rule deck development for 450nm tech node.training fresh engineers in the team
5)K2 rule deck debugging and fixing issues,K2 to assura rule deck porting for 450nm tech node
>Magic:
6)Rule deck development for online DRC,techfile of 180nm technode.
Porting of techfile from 350nm to 180nm,training fresh engineers
7)Testchips projects,Digital library development.555 timer,LDO projects,I/O Bufffer,simulations in excel and Power supply implementation,training fresh engineers,level converters
>Glade:
8)Porting of NCSU free PDK 45nm Calibre rule deck to Python rule deck ,Glade rule deck development for 180 nm,regression and training fresh engineers
>Perl:
9)Developed Pspice to Hspice conversion tool.
10)Trained fresh engineers for Perl automation and perl-tk.Perl script for creating inverter.
>Shell:
11)Trained fresh engineers for shell scripting
>Skill:
12)Skill scripting for automation.
>Pspice,Ngspice,LTspice
13)Coding and Digital library schematic verification