Harish Kumar K

Product Engineer

Mumbai, Maharashtra, India11 mos experience

Key Highlights

MTech Research at IIT Bombay in VLSI.
Achieved GATE25 AIR 577.
First Class with Distinction in UG-ECE.

Stackforce AI infers this person is a VLSI engineer with expertise in ASIC design and verification.

Contact

Skills

Core Skills

Application-specific Integrated Circuits (asic)Systemverilog

Other Skills

DebuggingUVMMixed-Signal Integrated CircuitsVLSI Design LabHigh Speed InterconnectsDigital Integrated Circuit DesignAnalog Integrated Circuit DesignSolid State PhysicsRTL DesignTest PlanningUniversal Verification Methodology (UVM)Digital CMOS VLSI DesignVerilog HDLAnalog ElectronicsDigital Electronics

About

I intend to establish myself as a VLSI professional looking forward to a long-term career in VLSI Domain, contributing to the company’s growth and thereby ensuring personal growth within the Organization.

Experience

11 mos

Total Experience

11 mos

Average Tenure

11 mos

Current Experience

Indian institute of technology, bombay

Research Assistant

Jul 2025 – Present · 11 mos · Mumbai, Maharashtra, India · On-site

Juniper networks

ASIC ENGINEER

Jan 2023 – Jun 2023 · 5 mos · Bengaluru, Karnataka, India · On-site

Created random and directed block level verification tests using System Verilog and UVM.
Worked on UVM DV Agents - Monitors ,Sequencers ,Scoreboards.
Regression scripting using Perl to check functionalities of the block.

DebuggingSystemVerilogApplication-Specific Integrated Circuits (ASIC)